CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
V
CCA
= V
CCD
= V
CCO
= +5V; V
RB
= 1.3V; V
RT
= 3.6V; T
A
= 25
o
C, Unless Otherwise Specified
TEST CONDITION
MIN
TYP
MAX
UNITS
CLOCK
(Referenced to DGND) (Note 2)
Logic Input Voltage Low, V
IL
Logic Input Voltage High, V
IH
Logic Input Current Low, I
IL
Logic Input Current High, I
IH
Input Impedance, Z
IN
Input Capacitance, C
IN
OE (Referenced to DGND)
Logic Input Voltage Low, V
IL
Logic Input Voltage High, V
IH
Logic Input Current Low, I
IL
Logic Input Current High, I
IH
V
IN
(Referenced to AGND)
Input Current Low, I
IL
Input Current High, I
IH
Input Impedance, Z
IN
Input Capacitance, C
IN
REFERENCE INPUT
Bottom Reference Range, V
RB
Top Reference Range, V
RT
Reference Range, V
REF
(V
RT
- V
RB
)
Reference Current, I
REF
Reference Ladder Resistance, R
LAD
R
LADTC
Bottom Offset Voltage, V
OB
V
OBTC
Top Offset Voltage, V
OT
V
OTTC
(Note 5)
(Note 5)
(Note 5)
(Note 5)
1.2
3.5
1.9
-
-
-
-
-
-
-
1.3
3.6
2.3
10
240
0.24
255
136
-300
480
1.6
3.9
2.7
-
-
-
-
-
-
-
V
V
V
mA
/
o
C
mV
V/
o
C
mV
V/
o
C
V
IN
= 1.2V
V
IN
= 3.5V
f
IN
= 4.43MHz
f
IN
= 4.43MHz
-
-
-
-
0
100
10
14
-
180
-
-
A
A
k
pF
V
IL
= 0.4V
V
IH
= 2.7V
0
2.0
-400
-
-
-
-
-
0.8
V
CCD
-
20
V
V
A
A
V
CLK
= 0.4V
V
CLK
= 2.7V
f
CLK
= 75MHz (Note 9)
f
CLK
= 75MHz (Note 9)
0
2.0
-400
-
-
-
-
-
-
-
2
4.5
0.8
V
CCD
-
300
-
-
V
V
A
A
k
pF
FN3973 Rev 6.00
July 2004
Page 3 of 14
HI5714
Electrical Specifications
PARAMETER
DIGITAL OUTPUTS
(D0 to D7 and O/UF Referenced to OGND)
Logic Output Voltage Low, V
OL
Logic Output Voltage High, V
OH
Output Leakage Current, I
D
Sample Rate, f
CLK
HI5714/7
HI5714/4
Clock Pulse Width High, t
CPH
Clock Pulse Width Low, t
CPL
ANALOG SIGNAL PROCESSING
(f
CLK
= 40MHz)
Differential Gain, DG
Differential Phase, DP
HARMONICS
(f
CLK
= 75MHz)
Second Harmonic, H2
Third Harmonic, H3
Total Harmonic Distortion, THD
Spurious Free Dynamic Range, SFDR
Analog Input Bandwidth (-3dB)
TRANSFER FUNCTION
Differential Linearity Error, DNL
Integral Linearity Error, INL
EFFECTIVE NUMBER OF BITS
ENOB
HI5714/4 (f
CLK
= 40MHz)
HI5714/7 (f
CLK
= 75MHz)
f
IN
= 4.43MHz
f
IN
= 7.5MHz
f
IN
= 4.43MHz
f
IN
= 7.5MHz
f
IN
= 10MHz
Bit Error Rate, BER
TIMING
(f
CLK
= 75MHz) See Figures 1, 2
Sampling Delay, t
SD
Output Hold Time, t
HD
Output Delay Time, t
D
Output Enable Delay, t
PZH
Output Enable Delay, t
PZL
Output Disable Delay, t
PHZ
Output Disable Delay, t
PLZ
Aperture Jitter, t
AJ
HI5714/4/7
Enable to High
Enable to Low
Disable from High
Disable from Low
-
5
-
-
-
-
-
-
-
-
10
14.6
17.8
5.3
6.7
50
2
-
13
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ps
(Note 8)
-
-
-
-
-
-
7.65
7.5
7.4
7.15
6.8
10
-11
-
-
-
-
-
-
Bits
Bits
Bits
Bits
Bits
Times/
Sample
(Note 7)
(Note 7)
-
-
0.4
0.75
-
-
LSB
LSB
f
IN
= 4.43MHz
f
IN
= 4.43MHz
f
IN
= 4.43MHz
f
IN
= 4.43MHz
-
-
-
-
-
-63
-65
-59
62
18
-
-
-
-
-
dB
dB
dB
dB
MHz
(Notes 6, 9)
(Notes 6, 9)
-
-
1.0
0.05
-
-
%
degree
75
40
6
6
-
-
-
-
-
-
-
-
MHz
MHz
ns
ns
I
O
= 1mA
I
O
= -0.4mA
0.4V < V
OUT
< V
CCO
0
2.7
-20
-
-
-
0.4
V
CCO
+20
V
V
A
V
CCA
= V
CCD
= V
CCO
= +5V; V
RB
= 1.3V; V
RT
= 3.6V; T
A
= 25
o
C, Unless Otherwise Specified
(Continued)
TEST CONDITION
MIN
TYP
MAX
UNITS
SWITCHING CHARACTERISTICS
(Notes 4, 5) See Figure 1
FN3973 Rev 6.00
July 2004
Page 4 of 14
HI5714
Electrical Specifications
PARAMETER
POWER SUPPLY CHARACTERISTICS
Analog Power Supply Range, V
CCA
Digital Power Supply Range, V
CCD
Output Power Supply Range, V
CCO
Total Supply Current
Supply Current, I
CCA
Supply Current, I
CCD
Supply Current, I
CCO
Power Dissipation
NOTES:
2. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.
3. The supply voltages V
CCA
and V
CCD
may have any value between -0.3V and +6V as long as the difference V
CCA
- V
CCD
lies between
-0.3V and +0.3V.
4. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock not be less than 1ns.
5. Analog input voltages producing code 00 up to and including FF. V
OB
(Bottom Offset Voltage) is the difference between the analog input which
produces data equal to 00 and the Bottom Reference Voltage (V
RB
). V
OBTC
(Bottom Offset Voltage Temperature Coefficient) is the variation
of V
OB
with temperature. V
OT
(Top Offset Voltage) is the difference between the Top Reference Voltage (V
RT
) and the analog input which
produces data output equal to FF. V
OTTC
(Top Offset Voltage Temperature Coefficient) is the variation of V
OT
with temperature.
6. Input is standard 5 step video test signal. A 12-bit R reconstruct DAC and VM700 are used for measurement.
7. Full scale sinewave, f
IN
= 4.43MHz.
8. f
CLK
= 75MHz, f
IN
= 4.43MHz, V
IN
=
8
LSB at code 128, 50% Clock duty cycle.
9. Parameter is guaranteed by design, not production tested.
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