CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
SYSTEM PERFORMANCE
Resolution
Integral Linearity Error, INL
Differential Linearity Error, DNL
Offset Error, I
OS
Offset Drift Coefficient
Full Scale Gain Error, FSE
AV
DD
= DV
DD
= +5V, V
REF
= Internal 1.2V, IOUTFS = 20mA, T
A
= 25
o
C for All Typical Values
T
A
= -40
o
C TO 85
o
C
TEST CONDITIONS
MIN
TYP
MAX
UNITS
8
“Best Fit” Straight Line (Note 7)
(Note 7)
(Note 7)
(Note 7)
With External Reference (Notes 2, 7)
With Internal Reference (Notes 2, 7)
-0.5
-0.5
-0.025
-
-10
-10
-
-
2
(Note 3)
-0.3
-
0.25
0.25
-
+0.5
+0.5
+0.025
Bits
LSB
LSB
% FSR
ppm
FSR/
o
C
% FSR
% FSR
ppm
FSR/
o
C
ppm
FSR/
o
C
mA
V
0.1
2
1
50
100
-
-
-
+10
+10
-
-
20
1.25
Full Scale Gain Drift
With External Reference (Note 7)
With Internal Reference (Note 7)
Full Scale Output Current, I
FS
Output Voltage Compliance Range
DYNAMIC CHARACTERISTICS
Maximum Clock Rate, f
CLK
Output Settling Time, (t
SETT
)
Singlet Glitch Area (Peak Glitch)
Output Rise Time
Output Fall Time
Output Capacitance
Output Noise
IOUTFS = 20mA
IOUTFS = 2mA
(Notes 3, 9)
0.8% (1 LSB, equivalent to 7 Bits) (Note 7)
0.4% (1/2 LSB, equivalent to 8 Bits) (Note 7)
R
L
= 25(Note 7)
Full Scale Step
Full Scale Step
125
-
-
-
-
-
-
5
15
5
1.5
1.5
10
-
-
-
-
-
-
MHz
ns
ns
pV•s
ns
ns
pF
-
-
50
30
-
-
pA/Hz
pA/Hz
FN4521 Rev 7.00
July 2004
Page 3 of 9
HI5660
Electrical Specifications
PARAMETER
AC CHARACTERISTICS
HI5660IB, HI5660IA - 125MHz
Spurious Free Dynamic Range,
SFDR Within a Window
Total Harmonic Distortion (THD) to
Nyquist
Spurious Free Dynamic Range,
SFDR to Nyquist
f
CLK
= 125MSPS, f
OUT
= 32.9MHz, 10MHz Span (Notes 4, 7)
f
CLK
= 100MSPS, f
OUT
= 5.04MHz, 4MHz Span (Notes 4, 7)
f
CLK
= 100MSPS, f
OUT
= 2.00MHz (Notes 4, 7)
f
CLK
= 125MSPS, f
OUT
= 32.9MHz, 62.5MHz Span (Notes 4, 7)
f
CLK
= 125MSPS, f
OUT
= 10.1MHz, 62.5MHz Span (Notes 4, 7)
f
CLK
= 100MSPS, f
OUT
= 40.4MHz, 50MHz Span (Notes 4, 7)
f
CLK
= 100MSPS, f
OUT
= 20.2MHz, 50MHz Span (Notes 4, 7)
f
CLK
= 100MSPS, f
OUT
= 5.04MHz, 50MHz Span (Notes 4, 7)
f
CLK
= 100MSPS, f
OUT
= 2.51MHz, 50MHz Span (Notes 4, 7)
AC CHARACTERISTICS
HI5660/6IA - 60MHz
Spurious Free Dynamic Range,
SFDR Within a Window
f
CLK
= 60MSPS, f
OUT
= 10.1MHz, 10MHz Span (Notes 4, 7)
f
CLK
= 50MSPS, f
OUT
= 5.02MHz, 2MHz Span (Notes 4, 7)
f
CLK
= 50MSPS, f
OUT
= 1.00MHz, 2MHz Span (Notes 4, 7)
Total Harmonic Distortion (THD) to
Nyquist
Spurious Free Dynamic Range,
SFDR to Nyquist
f
CLK
= 50MSPS, f
OUT
= 2.00MHz (Notes 4, 7)
f
CLK
= 50MSPS, f
OUT
= 1.00MHz (Notes 4, 7)
f
CLK
= 60MSPS, f
OUT
= 20.2MHz, 30MHz Span (Notes 4, 7)
f
CLK
= 60MSPS, f
OUT
= 10.1MHz, 30MHz Span (Notes 4, 7)
f
CLK
= 50MSPS, f
OUT
= 20.2MHz, 25MHz Span (Notes 4, 7)
f
CLK
= 50MSPS, f
OUT
= 5.02MHz, 25MHz Span (Notes 4, 7)
f
CLK
= 50MSPS, f
OUT
= 2.51MHz, 25MHz Span (Notes 4, 7)
f
CLK
= 50MSPS, f
OUT
= 1.00MHz, 25MHz Span (Notes 4, 7)
f
CLK
= 25MSPS, f
OUT
= 5.02MHz, 25MHz Span (Notes 4, 7)
VOLTAGE REFERENCE
Internal Reference Voltage, V
FSADJ
Internal Reference Voltage Drift
Internal Reference Output Current
Sink/Source Capability
Reference Input Impedance
Reference Input Multiplying Bandwidth (Note 7)
DIGITAL INPUTS
D7-D0, CLK
Input Logic High Voltage with
5V Supply, V
IH
Input Logic High Voltage with
3V Supply, V
IH
Input Logic Low Voltage with
5V Supply, V
IL
Input Logic Low Voltage with
3V Supply, V
IL
Input Logic Current, I
IH
Input Logic Current, I
IL
Digital Input Capacitance, C
IN
(Note 3)
(Note 3)
(Note 3)
(Note 3)
3.5
2.1
-
-
-10
-10
-
5
3
0
0
-
-
5
-
-
1.3
0.9
+10
+10
-
V
V
V
V
A
A
pF
Voltage at Pin 18 with Internal Reference
1.04
-
-
-
-
1.16
60
0.1
1
1.4
1.28
-
-
-
-
V
ppm
/
o
C
AV
DD
= DV
DD
= +5V, V
REF
= Internal 1.2V, IOUTFS = 20mA, T
A
= 25
o
C for All Typical Values
(Continued)
T
A
= -40
o
C TO 85
o
C
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
-
-
-
-
-
-
-
-
70
73
67
51
61
48
56
68
68
-
-
-
-
-
-
-
-
-
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
-
-
-
-
-
-
-
-
-
-
-
-
62
73
74
67
68
54
60
53
67
68
68
71
-
-
-
-
-
-
-
-
-
-
-
-
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
A
M
MHz
FN4521 Rev 7.00
July 2004
Page 4 of 9
HI5660
Electrical Specifications
PARAMETER
TIMING CHARACTERISTICS
Data Setup Time, t
SU
Data Hold Time, t
HLD
Propagation Delay Time, t
PD
CLK Pulse Width, t
PW1
, t
PW2
AV
DD
Power Supply
DV
DD
Power Supply
Analog Supply Current (I
AVDD
)
Digital Supply Current (I
DVDD
)
Supply Current (I
AVDD
) Sleep Mode
Power Dissipation
See Figure 3 (Note 3)
See Figure 3 (Note 3)
See Figure 3
See Figure 3 (Note 3)
3
3
-
4
-
-
1
-
-
-
-
-
ns
ns
ns
ns
AV
DD
= DV
DD
= +5V, V
REF
= Internal 1.2V, IOUTFS = 20mA, T
A
= 25
o
C for All Typical Values
(Continued)
T
A
= -40
o
C TO 85
o
C
TEST CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLY CHARACTERISTICS
(Note 8, 9)
(Note 8, 9)
5V or 3V, IOUTFS = 20mA
5V or 3V, IOUTFS = 2mA
5V, IOUTFS = Don’t Care (Note 5)
3V, IOUTFS = Don’t Care (Note 5)
5V or 3V, IOUTFS = Don’t Care
5V, IOUTFS = 20mA (Note 6)
5V, IOUTFS = 20mA (Note 10)
5V, IOUTFS = 2mA (Note 6)
3.3V, IOUTFS = 20mA (Note 10)
3V, IOUTFS = 20mA (Note 6)
3V, IOUTFS = 20mA (Note 10)
3V, IOUTFS = 2mA (Note 6)
Power Supply Rejection
NOTES:
2. Gain Error measured as the error in the ratio between the full scale output current and the current through R
SET
(typically 625A). Ideally the
ratio should be 32.
3. Parameter guaranteed by design or characterization and not production tested.
4. Spectral measurements made with differential transformer coupled output and no external filtering.
5. Measured with the clock at 50MSPS and the output frequency at 1MHz.
6. Measured with the clock at 100MSPS and the output frequency at 40MHz.
7. See ‘Definition of Specifications’.
8. It is recommended that the output current be reduced to 12mA or less to maintain optimum performance for operation below 3V. DV
DD
and AV
DD
do not have to be equal.
9. For operation above 125MHz, it is recommended that the power supply be 3.3V or greater. The part is functional with the clock above 125MSPS
and the power supply below 3.3V, but performance is degraded.
10. Measured with the clock at 60MSPS and the output frequency at 10MHz.
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
