Military & Space Products
32K x 8 STATIC RAM—Low Power SOI
FEATURES
RADIATION
• Fabricated with RICMOS
™
IV Silicon on Insulator (SOI)
0.55
µm
Low Power Process
• Total Dose Hardness through 1x10
6
rad(SiO
2
)
OTHER
• Read/Write Cycle Times
≤
17 ns (Typical)
≤
25 ns (-55 to 125°C)
HLX6256
• Typical Operating Power <10 mW/MHz
• Neutron Hardness through 1x10 cm
14
-2
• Asynchronous Operation
• Dynamic and Static Transient Upset Hardness
through 1x10
9
rad(Si)/s
• Dose Rate Survivability through 1x10
11
rad(Si)/s
• Single 3.3 V
±
0.3V Power Supply
• Soft Error Rate of <1x10
• Latchup Free
-10
• JEDEC Standard Low Voltage
CMOS Compatible I/O
upsets/bit-day
• Packaging Options
- 28-Lead Flat Pack (0.500 in. x 0.720 in.)
- 28-Lead DIP, MIL-STD-1835, CDIP2-T28
- 36-Lead Flat Pack (0.630 in. x 0.650 in.)
- Various Multi-Chip Module (MCM) Configurations
GENERAL DESCRIPTION
The 32K x 8 Radiation Hardened Static RAM is a high
performance 32,768 word x 8-bit static random access
memory with industry-standard functionality. It is fabri-
cated with Honeywell’s radiation hardened technology,
and is designed for use in low voltage systems operating in
radiation environments. The RAM operates over the full
military temperature range and requires only a single 3.3 V
±
0.3V power supply. The RAM is compatible with JEDEC
standard low voltage CMOS I/O. Power consumption is
typically less than 10 mW/MHz in operation, and less than
2 mW when de-selected. The RAM read operation is fully
asynchronous, with an associated typical access time of 14
ns at 3.3 V.
Honeywell’s enhanced SOI RICMOS
™
IV (Radiation Insen-
sitive CMOS) technology is radiation hardened through the
use of advanced and proprietary design, layout and pro-
cess hardening techniques. The RICMOS
™
IV low power
process is a SIMOX CMOS technology with a 150 Å gate
oxide and a minimum drawn feature size of 0.7
µm
(0.55
µm
effective gate length—L
eff
). Additional features include
tungsten via plugs, Honeywell’s proprietary SHARP pla-
narization process and a lightly doped drain (LDD) struc-
ture for improved short channel reliability. A 7 transistor
(7T) memory cell is used for superior single event upset
hardening, while three layer metal power bussing and the
low collection volume SIMOX substrate provide improved
dose rate hardening.
HLX6256
FUNCTIONAL DIAGRAM
A:0-8,12-13
Row
Decoder
•
•
•
11
32,768 x 8
Memory
Array
•
•
•
CE
NCS
Column Decoder
Data Input/Output
NWE
WE • CS • CE
8
8
DQ:0-7
NOE
NWE • CS • CE • OE
(0 = high Z)
Signal
1 = enabled
#
Signal
A:9-11, 14
4
All controls must be
enabled for a signal to
pass. (#: number of
buffers, default = 1)
SIGNAL DEFINITIONS
A: 0-14
DQ: 0-7
NCS
Address input pins which select a particular eight-bit word within the memory array.
Bidirectional data pins which serve as data outputs during a read operation and as data inputs during a write
operation.
Negative chip select, when at a low level allows normal read or write operation. When at a high level NCS
forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state and
disables all input buffers except CE. If this signal is not used it must be connected to VSS.
Negative write enable, when at a low level activates a write operation and holds the data output drivers in a
high impedance state. When at a high level NWE allows normal read operation.
Negative output enable, when at a high level holds the data output drivers in a high impedance state. When
at a low level, the data output driver state is defined by NCS, NWE and CE. If this signal is not used it must
be connected to VSS.
Chip enable, when at a high level allows normal operation. When at a low level CE forces the SRAM to a
precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers
except the NCS input buffer. If this signal is not used it must be connected to VDD.
NWE
NOE
CE*
TRUTH TABLE
NCS
L
L
H
X
CE*
H
H
X
L
NWE
H
L
XX
XX
NOE
L
X
XX
XX
MODE
Read
Write
Deselected
Disabled
DQ
Data Out
Data In
High Z
High Z
Notes:
X: VI=VIH or VIL
XX: VSS≤VI≤VDD
NOE=H: High Z output state maintained for
NCS=X, CE=X, NWE=X
*Not Available in 28-Lead DIP or 28-Lead Flat Pack
2
HLX6256
RADIATION CHARACTERISTICS
Total Ionizing Radiation Dose
The SRAM will meet all stated functional and electrical
specifications over the entire operating temperature range
after the specified total ionizing radiation dose. All electrical
and timing performance parameters will remain within
specifications after rebound at VDD = 3.6 V and T =125°C
extrapolated to ten years of operation. Total dose hardness
is assured by wafer level testing of process monitor transis-
tors and RAM product using 10 keV X-ray and Co60
radiation sources. Transistor gate threshold shift correla-
tions have been made between 10 keV X-rays applied at a
dose rate of 1x10
5
rad(SiO
2
)/min at T = 25°C and gamma
rays (Cobalt 60 source) to ensure that wafer level X-ray
testing is consistent with standard military radiation test
environments.
The SRAM will meet any functional or electrical specifica-
tion after exposure to a radiation pulse of up to the transient
dose rate survivability specification, when applied under
recommended operating conditions. Note that the current
conducted during the pulse by the RAM inputs, outputs and
power supply may significantly exceed the normal operat-
ing levels. The application design must accommodate
these effects.
Neutron Radiation
The SRAM will meet any functional or timing specification
after exposure to the specified neutron fluence under
recommended operating or storage conditions. This as-
sumes an equivalent neutron energy of 1 MeV.
Transient Pulse Ionizing Radiation
The SRAM is capable of writing, reading, and retaining
stored data during and after exposure to a transient
ionizing radiation pulse up to the transient dose rate upset
specification, when applied under recommended operat-
ing conditions. To ensure validity of all specified perfor-
mance parameters before, during, and after radiation
(timing degradation during transient pulse radiation (tim-
ing degradation during transient pulse radiation is
≤10%),
it is suggested that stiffening capacitance be placed on or
near the package VDD and VSS, with a maximum induc-
tance between the package (chip) and stiffening capaci-
tance of 0.7 nH per part. If there are no operate-through
or valid stored data requirements, typical circuit board
mounted de-coupling capacitors are recommended.
Soft Error Rate
The SRAM is immune to single event upsets (SEU’s) to the
specified soft error rate (SER), under recommended oper-
ating conditions. This hardness level is defined by the
Adams 10% worst case cosmic ray environment for geo-
synchronous orbits.
Latchup
The SRAM will not latch up due to any of the above
radiation exposure conditions when applied under recom-
mended operating conditions. Fabrication with the SIMOX
substrate material provides oxide isolation between adja-
cent PMOS and NMOS transistors and eliminates any
potential SCR latchup structures. Sufficient transistor
body tie connections to the p- and n-channel substrates
are made to ensure no source/drain snapback occurs.
RADIATION HARDNESS RATINGS (1)
Parameter
Total Dose
Transient Dose Rate Upset (3)
Transient Dose Rate Survivability (3)
Soft Error Rate (SER)
Neutron Fluence
Limits (2)
≥1x10
6
≥1x10
9
≥1x10
11
<1x10
-10
≥1x10
14
Units
rad(SiO
2
)
rad(Si)/s
rad(Si)/s
upsets/bit-day
N/cm
2
Test Conditions
T
A
=25°C
Pulse width
≤1 µs
Pulse width
≤50
ns, X-ray,
VDD=4.0 V, T
A
=25°C
T
A
=125°C, Adams 10%
worst case environment
1 MeV equivalent energy,
Unbiased, T
A
=25°C
(1) Device will not latch up due to any of the specified radiation exposure conditions.
(2) Operating conditions (unless otherwise specified): VDD=3.0 V to 3.6 V, TA=-55°C to 125°C.
(3) Not guaranteed with 28–Lead DIP.
3
HLX6256
ABSOLUTE MAXIMUM RATINGS
(1)
Rating
Symbol
VDD
VPIN
TSTORE
TSOLDER
PD
IOUT
VPROT
Parameter
Positive Supply Voltage (2)
Voltage on Any Pin (2)
Storage Temperature (Zero Bias)
Soldering Temperature • Time
Total Package Power Dissipation (3)
DC or Average Output Current
ESD Input Protection Voltage (4)
28 FP/36 FP
Thermal Resistance (Jct-to-Case)
Junction Temperature
28 DIP
2000
2
10
175
Min
-0.5
-0.5
-65
Max
6.5
VDD+0.5
150
270•5
2.0
2.0
Units
V
V
°C
°C•s
W
mA
V
°C/W
°C
Θ
JC
TJ
(1) Stresses in excess of those listed above may result in permanent damage. These are stress ratings only, and operation at these levels is not
implied. Frequent or extended exposure to absolute maximum conditions may affect device reliability.
(2) Voltage referenced to VSS.
(3) RAM power dissipation (IDDSB + IDDOP) plus RAM output driver power dissipation due to external loading must not exceed this specification.
(4) Class 2 electrostatic discharge (ESD) input protection. Tested per MIL-STD-883, Method 3015 by DESC certified lab.
RECOMMENDED OPERATING CONDITIONS
Description
Symbol
VDD
TA
VPIN
Parameter
Supply Voltage (referenced to VSS)
Ambient Temperature
Voltage on Any Pin (referenced to VSS)
Min
3.0
-55
-0.3
Typ
3.3
25
Max
3.6
125
VDD+0.3
Units
V
°C
V
CAPACITANCE
(1)
Symbol
CI
CO
Parameter
Input Capacitance
Output Capacitance
Typical
(1)
Worst Case
Min
Max
7
9
Units
pF
pF
Test Conditions
VI=VDD or VSS, f=1 MHz
VIO=VDD or VSS, f=1 MHz
(1) This parameter is tested during initial design characterization only.
DATA RETENTION CHARACTERISTICS
Symbol
VDR
IDR
Parameter
Data Retention Voltage
Data Retention Current
Typical
(1)
Worst Case
(2)
Units
Min
1.65
300
Max
V
µA
NCS=VDR
VI=VDR or VSS
NCS=VDD=VDR
VI=VDR or VSS
Test Conditions
(1) Typical operating conditions: TA= 25°C, pre-radiation.
(2) Worst case operating conditions: TA= -55°C to +125°C, post total dose at 25°C.
4
HLX6256
DC ELECTRICAL CHARACTERISTICS
Symbol
IDDSB1
Parameter
Static Supply Current
Typical Worst Case (2)
Units
(1)
Min
Max
1.0
1.0
3.0
3.0
-1
-1
-0.3
+1
+1
0.3xV
DD
Test Conditions
VIH=VDD IO=0
VIL=VSS Inputs Stable
NCS=VDD, IO=0,
f=40 MHz
f=1 MHz, IO=0, CE=VIH=VDD
NCS=VIL=VSS
f=1 MHz, IO=0, CE=VIH=VDD
NCS=VIL=VSS
VSS≤VI≤VDD
VSS≤VIO≤VDD
Output=high Z
March Pattern
VDD = 3.0V
March Pattern
VDD = 3.6V
VDD = 3.0V, IOL = 8 mA
mA
mA
mA
mA
µA
µA
V
V
V
V
V
IDDSBMF Standby Supply Current - Deselected
IDDOPW
IDDOPR
II
IOZ
VIL
Dynamic Supply Current, Selected
(Write)
Dynamic Supply Current, Selected
(Read)
Input Leakage Current
Output Leakage Current
Low-Level Input Voltage
VIH
High-Level Input Voltage
0.7xV
DD
V
DD
+.3
VOL
Low-Level Output Voltage
2.7
0.4
VOH
High-Level Output Voltage
V
VDD = 3.0V, IOH = -4 mA
(1) Typical operating conditions: VDD=3.3 V, TA=25°C, pre-radiation.
(2) Worst case operating conditions: VDD=3.0 V to 3.6 V, TA=-55°C to +125°C, post total dose at 25°C.
(3) All inputs switching. DC average current.
2.2 V
Vref1
249Ω
DUT
output
Vref2
+
-
Valid high
output
+
-
Valid low
output
CL >50 pF*
*CL = 5 pF for TWLQZ, TSHQZ, TELQZ, and TGHQZ
Tester Equivalent Load Circuit
5
ARM技术
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
