HM5212165F-75/A60/B60
HM5212805F-75/A60/B60
128M LVTTL interface SDRAM
133 MHz/100 MHz
2-Mword
×
16-bit
×
4-bank/4-Mword
×
8-bit
×
4-bank
PC/133, PC/100 SDRAM
ADE-203-1048A (Z)
Rev. 1.0
Jan. 31, 2000
Description
The Hitachi HM5212165F is a 128-Mbit SDRAM organized as 2097152-word
×
16-bit
×
4-bank. The
Hitachi HM5212805F is a 128-Mbit SDRAM organized as 4194304-word
×
8-bit
×
4-bank. All inputs and
outputs are referred to the rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP II.
Features
3.3 V power supply
Clock frequency: 133 MHz/100 MHz (max)
LVTTL interface
Single pulsed
RAS
4 banks can operate simultaneously and independently
Burst read/write operation and burst read/single write operation capability
Programmable burst length: 1/2/4/8/full page
2 variations of burst sequence
Sequential (BL = 1/2/4/8/full page)
Interleave (BL = 1/2/4/8)
•
Programmable
CAS
latency: 2/3
•
Byte control by DQM : DQM (HM5212805F)
: DQMU/DQML (HM5212165F)
•
Refresh cycles: 4096 refresh cycles/64 ms
•
•
•
•
•
•
•
•
HM5212165F/HM5212805F-75/A60/B60
•
2 variations of refresh
Auto refresh
Self refresh
•
Full page burst length capability
Sequential burst
Burst stop capability
Ordering Information
Type No.
HM5212165FTD-75*
1
HM5212165FTD-A60
HM5212165FTD-B60*
2
HM5212165FLTD-75*
1
HM5212165FLTD-A60
HM5212165FLTD-B60*
2
HM5212805FTD-75*
1
HM5212805FTD-A60
HM5212805FTD-B60*
2
HM5212805FLTD-75*
1
HM5212805FLTD-A60
HM5212805FLTD-B60*
2
Frequency
133 MHz
100 MHz
100 MHz
133 MHz
100 MHz
100 MHz
133 MHz
100 MHz
100 MHz
133 MHz
100 MHz
100 MHz
CAS
latency
3
2/3
3
3
2/3
3
3
2/3
3
3
2/3
3
Package
400-mil 54-pin plastic TSOP II (TTP-54DA)
Notes: 1. 100 MHz operation at
CAS
latency = 2.
2. 66 MHz operation at
CAS
latency = 2.
2
HM5212165F/HM5212805F-75/A60/B60
Pin Arrangement
(HM5212165F)
54-pin TSOP
V
CC
DQ0
V
CC
Q
DQ1
DQ2
V
SS
Q
DQ3
DQ4
V
CC
Q
DQ5
DQ6
V
SS
Q
DQ7
V
CC
DQML
WE
CAS
RAS
CS
A13
A12
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
(Top view)
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ15
V
SS
Q
DQ14
DQ13
V
CC
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
CC
Q
DQ8
V
SS
NC
DQMU
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
Pin Description
Pin name
A0 to A13
Function
Address input
Row address
Column address
DQ0 to DQ15
CS
RAS
CAS
WE
Data-input/output
Chip select
Row address strobe command
Column address strobe command
Write enable
A0 to A11
A0 to A8
Pin name
DQMU/DQML
CLK
CKE
Function
Input/output mask
Clock input
Clock enable
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Bank select address A12/A13 (BS) V
CC
V
SS
V
CC
Q
V
SS
Q
NC
3
HM5212165F/HM5212805F-75/A60/B60
Pin Arrangement
(HM5212805F)
54-pin TSOP
V
CC
DQ0
V
CC
Q
NC
DQ1
V
SS
Q
NC
DQ2
V
CC
Q
NC
DQ3
V
SS
Q
NC
V
CC
NC
WE
CAS
RAS
CS
A13
A12
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
(Top view)
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ7
V
SS
Q
NC
DQ6
V
CC
Q
NC
DQ5
V
SS
Q
NC
DQ4
V
CC
Q
NC
V
SS
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
Pin Description
Pin name
A0 to A13
Function
Address input
Row address
Column address
DQ0 to DQ7
CS
RAS
CAS
WE
Data-input/output
Chip select
Row address strobe command
Column address strobe command
Write enable
A0 to A11
A0 to A9
Pin name
DQM
CLK
CKE
Function
Input/output mask
Clock input
Clock enable
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Bank select address A12/A13 (BS) V
CC
V
SS
V
CC
Q
V
SS
Q
NC
4
HM5212165F/HM5212805F-75/A60/B60
Block Diagram
(HM5212165F)
A0 to A13
Upper pellet
A0 to A8
Column address
counter
Column address
buffer
A0 to A13
Row address
buffer
Refresh
counter
Row decoder
Sense amplifier & I/O bus
Sense amplifier & I/O bus
Row decoder
Sense amplifier & I/O bus
Row decoder
Sense amplifier & I/O bus
Row decoder
Memory array
Column decoder
Bank0
4096 row
×
512 column
×
8 bit
Memory array
Column decoder
Bank1
4096 row
×
512 column
×
8 bit
Memory array
Bank2
4096 row
×
512 column
×
8 bit
Column decoder
Memory array
Bank3
4096 row
×
512 column
×
8 bit
Column decoder
Input buffer
Output buffer
CLK
CKE
Control logic &
timing generator
CS
RAS
CAS
WE
DQMU
/DQML
DQ8 to DQ15
DQ0 to DQ7
Input buffer
Output buffer
Sense amplifier & I/O bus
Sense amplifier & I/O bus
Sense amplifier & I/O bus
Sense amplifier & I/O bus
Memory array
Column decoder
Bank0
4096 row
×
512 column
×
8 bit
Memory array
Column decoder
Bank1
4096 row
×
512 column
×
8 bit
Memory array
Column decoder
Bank2
4096 row
×
512 column
×
8 bit
Memory array
Bank3
4096 row
×
512 column
×
8 bit
Column decoder
Row decoder
Row decoder
Row decoder
Row decoder
Column address
counter
Column address
buffer
Row address
buffer
Refresh
counter
Lower pellet
5
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