HM6268 Series
4096-word
×
4-bit High-Speed CMOS Static RAM
Maintenance only
Features
• Single 5 V supply and high density 20-pin
package
• High speed: fast access time 25/35/45 ns (max)
• Low power
— Active: 250 mW (typ)
— Standby: 100 µW (typ), 5 µW (typ)
(L-version)
• Completely static memory: no clock or timing
strobe required
• Equal access and cycle times
• Directly TTL compatible—all inputs and outputs
• Battery back-up operation capability
(L-version)
Pin Arrangement
A4
A5
A6
A7
A8
A9
A10
A11
CS
V
SS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
A3
A2
A1
A0
I/O1
I/O2
I/O3
I/O4
WE
(Top view)
Ordering Information
Type No.
HM6268P-25
HM6268P-35
HM6268P-45
HM6268LP-25
HM6268LP-35
HM6268LP-45
Access time
25 ns
35 ns
45 ns
25 ns
35 ns
45 ns
Package
300-mil 20-pin, plastic DIP
(DP-20N)
Note: This device is not available for new application.
1
HM6268 Series
Block Diagram
HM6268 Series
A10
A4
A5
A6
A7
A8
I/O1
I/O2
I/O3
I/O4
A0 A1 A2 A3 A11 A9
Input
data
control
Row
decoder
Memory array
64
×
256
V
CC
V
SS
Column I/O
Column decoder
CS
WE
Truth Table
CS
H
L
L
WE
x
H
L
Mode
Not Selected
Read
Write
V
CC
current
I
SB
, I
SB1
I
CC
I
CC
I/O pin
High-Z
Dout
Din
Cycle
—
Read cycle
Write cycle
Absolute Maximum Ratings
Parameter
Voltage on any pin relative to V
SS
Power dissipation
Operating temperature
Storage temperature
Temperature under bias
Note:
Symbol
V
T
P
T
Topr
Tstg
Tbias
Rating
–0.5
*1
to +7.0
1.0
0 to + 70
–55 to +125
–10 to + 85
Unit
V
W
°C
°C
°C
1. –3.5 V for pulse width
≤
10 ns.
2
HM6268 Series
Recommended DC Operating Conditions
(Ta = 0 to + 70°C)
Parameter
Supply voltage
Symbol
V
CC
V
SS
Input high (logic 1) voltage
Input low (logic 0) voltage
Note:
V
IH
V
IL
Min
4.5
0
2.2
–0.5
*1
Typ
5.0
0
—
—
Max
5.5
0
6.0
0.8
Unit
V
V
V
V
HM6268 Series
1. –3.0 V for pulse width
≤
10 ns.
DC Characteristics
(V
CC
= 5 V ± 10%, V
SS
= 0 V, Ta = 0 to +70°C)
Parameter
Input leakage current
Symbol
| I
LI
|
Min
—
—
Typ
*1
—
—
Max
2.0
Unit
µA
Test condition
V
CC
= 5.5 V,
Vin = V
SS
to V
CC
CS
= V
IH
,
V
I/O
= V
SS
to V
CC
CS
= V
IL
, I
I/O
= 0 mA,
min. cycle
CS
= V
IH
, min. cycle
CS
≥
V
CC
– 0.2 V,
0 V
≤
V
IN
≤
0.2 V or
V
CC
– 0.2 V
≤
V
IN
I
OL
= 8 mA
I
OH
= –4.0 mA
Output leakage current
| I
LO
|
2.0
µA
Operating power supply current
I
CC
—
50
*3
90
mA
Standby power supply current
I
SB
—
—
—
15
0.02
1
*2
25
2.0
50
*2
mA
mA
µA
Standby power supply current (1) I
SB1
Output low voltage
Output high voltage
V
OL
V
OH
—
2.4
—
—
0.4
—
V
V
Notes: 1. Typical limits are at V
CC
= 5.0 V, Ta = +25°C and specified loading
2. This characteristic is guaranteed only for L-version.
3. 40 mA typical for 45 ns version.
Capacitance
(Ta = 25°C, f = 1.0 MHz)
*1
Parameter
Input capacitance
Input/output capacitance
Note:
Symbol Test conditions
Cin
C
I/O
Vin = 0 V
V
I/O
= 0 V
Min
—
—
Max
6
9
Unit
pF
pF
1. These parameters are sampled and not 100% tested.
3
HM6268 Series
AC Test Conditions:
•
•
•
•
Input pulse levels: V
SS
to 3.0 V
Input rise and fall times: 5 ns
Input and output timing reference levels: 1.5 V
Output load: See figure
HM6268 Series
AC Characteristics
(V
CC
= 5 V + 10%, Ta = 0 to +70°C, unless otherwise noted)
Output Load
5V
480
Ω
5V
480
Ω
Dout
255
Ω
Dout
255
Ω
30 pF
*1
5 pF
*1
Output load (A)
Output load (B)
(t
HZ
, t
LZ
, t
WZ,
and t
OW
)
Note: 1. Including scope and jig
Read Cycle
HM6268-25 HM6268-35 HM6268-45
—————— —————— ——————
Symbol Min
Max Min
Max Min
Max Unit
t
RC
t
AA
t
ACS
t
OH
t
LZ *1
t
HZ *1
25
—
—
5
—
25
25
—
35
—
—
5
—
35
35
—
45
—
—
5
—
45
45
—
ns
ns
ns
ns
Parameter
Read cycle time
Address access time
Chip select access time
Output hold from address
change
Chip selection to output in low-Z
Chip deselection to output in
high-Z
Chip selection to power up time
Chip deselection to power down
time
Note:
10
0
—
15
10
0
—
20
10
0
—
20
ns
ns
t
PU
t
PD
0
—
—
25
0
—
—
25
0
—
—
30
ns
ns
1. Transition is measured +200 mV from steady state voltage with load (B).
These parameters are sampled and not 100% tested.
4
HM6268 Series
Read Timing Waveform (1)
t
RC
Address
t
AA
t
OH
Dout
Valid Data
t
OH
HM6268 Series
Notes: 1.
WE
is high for read cycle.
2. Device is continuously selected,
CS
= V
IL
Read Timing Waveform (2)
t
RC
CS
t
LZ
t
ACS
t
HZ
Valid Data
t
PD
50%
High
impedance
Dout
V
CC
Supply
current
High impedance
t
PU
I
CC
I
SB
50%
Notes: 1.
WE
is high for read cycle.
2. Address valid prior to or coincident with
CS
transistion low.
5
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