HANBit
HAN
BIT
HMS25632M8B/Z8B
SRAM MODULE 1Mbyte (256K x 32-Bit) , 72-Pin
Part No.
HMS25632M8B, HMS25632Z8B
GENERAL DESCRIPTION
The HMS25632M8B is a high-speed static random access memory (SRAM) module containing 262,144 words
organized in a x32-bit configuration. The module consists of eight 256K x 4 SRAMs mounted on a 72-pin, double-
sided, FR4-printed circuit board.
PD0 to PD3 identify the module’s density allowing interchangeable use of alternate density, industry- standard
modules. Eight chip enable inputs, (/CE1, /CE2, /CE3 and /CE4) are used to enable the module’s 4 bytes
independently. Output enable (/OE) and write enable(/WE) can set the memory input and output.
Data is written into the SRAM memory when write enable (/WE) and chip enable (/CE) inputs are both LOW.
Reading is accomplished when /WE remains HIGH and /CE and output enable (/OE) are LOW.
For reliability, this SRAM module is designed as multiple power and ground pin. All module components may be
powered from a single +5V DC power supply and all inputs and outputs are fully TTL-compatible.
FEATURES
Access times : 8, 10,12, 15 and 20ns
High-density 1MByte design
High-reliability high-speed design
Single + 5V
±0.5V
power supply
Easy memory expansion /CE and /OE functions
All inputs and outputs are TTL-compatible
Industry-standard pinout
FR4-PCB design
Part identification
- HMS25632M8B : 72-pin SIMM design
- HMS25632Z8B : 72-pin ZIP design
→
Pin-compatible with the HMS25632M8B
NC
NC
PD2
PD3
Vss
PD0
PD1
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
Vcc
A0
A7
A1
A8
A2
A9
DQ12
DQ4
DQ13
DQ5
DQ14
DQ6
DQ15
DQ7
Vss
/WE
A15
A14
/CE2
/CE1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
PIN ASSIGNMENT
/CE4
/CE3
A17
A16
/OE
Vss
DQ24
DQ16
DQ25
DQ17
DQ26
DQ18
DQ27
DQ19
A3
A10
A4
A11
A5
A12
Vcc
A13
A6
DQ20
DQ28
DQ21
DQ29
DQ22
DQ30
DQ23
DQ31
Vss
NC
NC
NC
NC
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
OPTIONS
Timing
10
n
s access
12
n
s access
15
n
s access
20
n
s access
MARKING
-10
-12
-15
-20
M
Z
Packages
72-pin SIMM
72-pin ZIP
PD0 = Vss
72-Pin
SIMM
PD1 = Vss
PD2 = Open
TOP VIEW
PD3 = Open
1
HANBit Electronics Co.,Ltd.
HANBit
FUNCTIONAL BLOCK DIAGRAM
32
18
A0-17
DQ 0-3
/WE
/OE
HMS25632M8B/Z8B
DQ0 - DQ31
A0 - A17
A0-17
DQ 4-7
/WE
/OE
U1
/CE
U5
/CE
/CE1
A0-17
DQ 8-11
/WE
/OE
/WE
A0-17
DQ12-15
/OE
U2
/CE
U6
/CE
/CE2
A0-17
DQ16-19
/WE
/OE
/WE
A0-17
DQ20-23
/OE
U3
/CE
U7
/CE
/CE3
A0-17
/WE
/OE
DQ24-27
/WE
/OE
/WE
A0-17
DQ28-31
/OE
U4
/CE
U8
/CE
/CE4
MODE
STANDBY
NOT SELECTED
READ
WRITE
/OE
X
H
L
X
/CE
H
L
L
L
/WE
X
H
H
L
OUTPUT
HIGH-Z
HIGH-Z
Dout
Din
POWER
STANDBY
ACTIVE
ACTIVE
ACTIVE
2
HANBit Electronics Co.,Ltd.
HANBit
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Voltage on Any Pin Relative to Vss
Voltage on Vcc Supply Relative to Vss
Power Dissipation
Storage Temperature
SYMBOL
V
IN,OUT
V
CC
P
D
T
STG
HMS25632M8B/Z8B
RATING
-0.5V to Vcc+0.5V
-0.5V to +7.0V
8W
-65oC to +150oC
Operating Temperature
T
A
0oC to +70oC
Stresses greater than those listed under " Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated
in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
*
SYMBOL
V
CC
V
SS
V
IH
V
IL
MIN
4.5V
0
2.2
-0.5*
( TA=0 to 70 o C )
TYP.
5.0V
0
-
-
MAX
5.5V
0
Vcc+0.5V**
0.8V
V
IL
(Min.) = -2.0V (Pulse Width
≤
10ns) for I
≤
20 mA
**
V
IH
(Min.) = Vcc+2.0V (Pulse Width
≤
10ns) for I
≤
20 mA
DC AND OPERATING CHARACTERISTICS (1)
(0oC
≤
TA
≤
70 oC ; Vcc = 5V
±
0.5V )
PARAMETER
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
* Vcc=5.0V, Temp=25 oC
TEST CONDITIONS
V
IN
= Vss to Vcc
/CE=V
IH or /
OE =V
IH
or /WE=V
IL
V
OUT
=Vss to V
CC
I
OH
= -4.0Ma
I
OL
= 8.0mA
SYMBO
L
IL
I
IL
0
V
OH
V
OL
MIN
-2
-2
2.4
0.4
MAX
2
2
UNITS
µA
µA
V
V
DC AND OPERATING CHARACTERISTICS (2)
MAX
DESCRIPTION
Power Supply
Current: Operating
Power Supply
Current: Standby
TEST CONDITIONS
Min. Cycle, 100% Duty
/CE=V
IL
, V
IN
=V
IH
or V
IL
,
I
OUT
=0mA
Min. Cycle, /CE=V
IH
f=0MHZ, /CE≥V
CC
-0.2V,
V
IN
≥
V
CC
-0.2V or V
IN
≤0.2V
SYMBOL
I
CC
I
SB
I
SB1
-12
70
30
5
-15
68
30
5
-20
65
30
5
UNIT
mA
mA
mA
3
HANBit Electronics Co.,Ltd.
HANBit
CAPACITANCE
DESCRIPTION
Input /Output Capacitance
Input Capacitance
TEST CONDITIONS
V
I/O
=0V
V
IN
=0V
SYMBOL
C
I/O
C
IN
HMS25632M8B/Z8B
MAX
8
6
UNIT
pF
pF
*
NOTE
: Capacitance is sampled and not 100% tested
AC CHARACTERISTICS
(0oC
≤
TA
≤
70 oC ; Vcc = 5V
±
0.5V, unless otherwise specified)
TEST CONDITIONS
PARAMETER
Input Pulse Level
Input Rise and Fall Time
Input and Output Timing Reference Levels
Output Load
VALUE
0 to 3V
3ns
1.5V
See below
Output
+5V
Load
Output Load (B)
for t
HZ
, t
LZ
, t
WHZ
, t
OW
, t
OLZ
& t
OHZ
+5V
480
Ω
D
OUT
255
Ω
30pF*
D
OUT
255
Ω
480
Ω
5pF*
READ CYCLE
-12
PARAMETER
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Output
Output Enable to Low-Z Output
Chip Enable to Low-Z Output
Output Disable to High-Z Output
Chip Disable to High-Z Output
Output Hold from Address Change
Chip Select to Power Up Time
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
-15
-20
UNIT
t
RC
t
AA
t
CO
t
OE
t
OLZ
t
LZ
t
OHZ
t
HZ
t
OH
t
PU
12
12
12
6
0
3
0
0
3
-
6
6
15
15
15
7
0
3
0
0
3
0
7
7
20
20
20
9
0
3
0
0
3
0
HANBit Electronics Co.,Ltd.
ns
ns
ns
ns
ns
ns
9
9
ns
ns
ns
ns
4
HANBit
Chip Select to Power Down Time
t
PD
-
12
HMS25632M8B/Z8B
15
20
ns
WRITE CYCLE
-12
PARAMETER
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End of Write to Output Low-Z
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
-15
-20
UNIT
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
12
8
0
8
8
0
0
6
0
3
6
15
9
0
9
9
0
0
7
0
3
7
20
10
0
10
10
0
0
8
0
5
9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE
( Address Controlled) ( /CE = /OE = V
IL
, /WE = V
IH
)
t
RC
Address
t
AA
t
OH
Data out
Previous Data Valid
Data Valid
5
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