DATASHEET
HS-80C86RH
Radiation Hardened 16-Bit CMOS Microprocessor
The Intersil HS-80C86RH high performance radiation
hardened 16-bit CMOS CPU is manufactured using a
hardened field, self aligned silicon gate CMOS process. Two
modes of operation, MINimum for small systems and
MAXimum for larger applications such as multiprocessing,
allow user configuration to achieve the highest performance
level. Industry standard operation allows use of existing
NMOS 8086 hardware and software designs.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed here must be used when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD 5962-95722. A “hot-link” is provided
on our homepage for downloading.
www.intersil.com/spacedefense/space.asp
FN3035
Rev 0.00
August 2000
Features
• Electrically Screened to SMD # 5962-95722
• QML Qualified per MIL-PRF-38535 Requirements
• Radiation Performance
- Latch Up Free EPl-CMOS
- Total Dose. . . . . . . . . . . . . . . . . . . . . 100 krad(Si) (Max)
- Transient Upset . . . . . . . . . . . . . . . . . . . .>10
8
rad(Si)/s
• Low Power Operation
- ICCSB. . . . . . . . . . . . . . . . . . . . . . . . . . . . .500A (Max)
- ICCOP . . . . . . . . . . . . . . . . . . . . . . . 12mA/MHz (Max)
• Pin Compatible with NMOS 8086 and Intersil 80C86
• Completely Static Design DC to 5MHz
• 1MB Direct Memory Addressing Capability
• 24 Operand Addressing Modes
Ordering Information
ORDERING NUMBER
5962R9572201QQC
5962R9572201QXC
5962R9572201VQC
5962R9572201VXC
HS1-80C86RH/Proto
HS9-80C86RH/Proto
INTERNAL
MKT. NUMBER
HS1-80C86RH-8
HS9-80C86RH-8
HS1-80C86RH-Q
HS9-80C86RH-Q
HS1-80C86RH/Proto
HS9-80C86RH/Proto
TEMP. RANGE
(
o
C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
• Bit, Byte, Word, and Block Move Operations
• 8-Bit and 16-Bit Signed/Unsigned Arithmetic
- Binary or Decimal
- Multiply and Divide
• Bus-Hold Circuitry Eliminates Pull-up Resistors for CMOS
Designs
• Hardened Field, Self-Aligned, Junction-Isolated CMOS
Process
• Single 5V Power Supply
• Military Temperature Range . . . . . . . . . . . -35
o
C to 125
o
C
• Minimum LET for
Single Event Upset . . . . . . . . . . . . . 6MEV/mg/cm
2
(Typ)
FN3035 Rev 0.00
August 2000
Page 1 of 30
HS-80C86RH
Pinout
HS-80C86RH 40 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835, CDIP2-T40
TOP VIEW
MAX
40 VDD
39 AD15
38 AD16/S3
37 A17/S4
36 A18/S5
35 A19/S6
34 BHE/S7
33 MN/MX
32 RD
31 RQ/GT0
30 RQ/GT1
29 LOCK
28 S2
27 S1
26 S0
25 QS0
24 QS1
23 TEST
22 READY
21 RESET
(HOLD)
(HLDA)
(WR)
(M/IO)
(DT/R)
(DEN)
(ALE)
(INTA)
MIN
GND
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NMI
INTR
CLK
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
HS-80C86RH 42 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK)
INTERSIL OUTLINE K42.A
TOP VIEW
MAX
VDD
AD15
NC
A16/S3
A17/S4
A18/S5
A19/S6
BHE/S7
MN/MX
RD
RQ/GT0
RQ/GT1
LOCK
S2
S1
S0
QS0
QS1
TEST
READY
RESET
MIN
GND
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NC
NMI
INTR
CLK
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
(HOLD)
(HLDA)
(WR)
(M/IO)
(DT/R)
(DEN)
(ALE)
(INTA)
FN3035 Rev 0.00
August 2000
Page 2 of 30
HS-80C86RH
Functional Diagram
EXECUTION UNIT
REGISTER FILE
DATA POINTER
AND
INDEX REGS
(8 WORDS)
BUS INTERFACE UNIT
RELOCATION
REGISTER FILE
SEGMENT REGISTERS
AND
INSTRUCTION POINTER
(5 WORDS)
16-BIT ALU
FLAGS
BUS INTERFACE UNIT
4
16
3
4
BHE/S7
A19/S6
A16/S3
AD15-AD0
INTA, RD, WR
DT/R, DEN, ALE, M/IO
6-BYTE
INSTRUCTION
QUEUE
TEST
INTR
NMI
RQ/GT0, 1
HOLD
HLDA
3
GND
VDD
2
CONTROL AND TIMING
LOCK
2
3
QS0, QS1
S2, S1, S0
CLK
RESET READY MN/MX
MEMORY INTERFACE
C-BUS
B+BUS
ES
BUS
INTERFACE
UNIT
CS
SS
DS
IP
INSTRUCTION
STREAM BYTE
QUEUE
EXECUTION UNIT
CONTROL SYSTEM
A-BUS
AH
BH
CH
EXECUTION
UNIT
DH
SP
BP
SI
DI
AL
BL
CL
DL
ARITHMETIC/
LOGIC UNIT
FLAGS
FN3035 Rev 0.00
August 2000
Page 3 of 30
HS-80C86RH
Pin Descriptions
SYMBOL
PIN
NUMBER
TYPE
DESCRIPTION
The following pin function descriptions are for HS-80C86RH systems in either minimum or maximum mode. The “Local Bus” in these descriptions
is the direct multiplexed bus interface connection to the HS-80C86RH (without regard to additional bus buffers).
AD15-AD0
2-16, 39
I/O
ADDRESS DATA BUS: These lines constitute the time multiplexed memory/IO address (T1) and data
(T2, T3, TW, T4) bus. AO is analogous to BHE for the lower byte of the data bus, pins D7-D0. It is LOW
during T1 when a byte is to be transferred on the lower portion of the bus in memory or I/O operations.
Eight-bit oriented devices tied to the lower half would normally use AD0 to condition chip select functions
(See BHE). These lines are active HIGH and are held at high impedance to the last valid logic level during
interrupt acknowledge and local bus “hold acknowledge” or “grant sequence”.
ADDRESS/STATUS: During T1, these are the four most significant address lines for memory operations.
During I/O operations these lines are low. During memory and I/O operations, status information is
available on these lines during T2, T3, TW, T4. S6 is always zero. The status of the interrupt enable FLAG
bit (S5) is updated at the beginning of each CLK cycle. S4 and S3 are encoded.
This information indicates which segment register is presently being used for data accessing. These lines
are held at high impedance to the last valid logic level during local bus “hold acknowledge” or “grant
sequence”.
S4
0
0
1
1
BHE/S7
34
O
S3
0
1
0
1
Extra Data
Stack
Code or None
Data
A19/S6
A18/S5
A17/S4
A16/S3
35-38
O
BUS HIGH ENABLE/STATUS: During T1 the bus high enable signal (BHE) should be used to enable
data onto the most significant half of the data bus, pins D15-D8. Eight bit oriented devices tied to the
upper half of the bus would normally use BHE to condition chip select functions. BHE is LOW during T1
for read, write, and interrupt acknowledge cycles when a byte is to be transferred on the high portion of
the bus. The S7 status information is available during T2, T3 and T4. The signal is active LOW, and is
held at high impedance to the last valid logic level during interrupt acknowledge and local bus “hold
acknowledge” or “grant sequence”; it is LOW during T1 for the first interrupt acknowledge cycle.
BHE
0
0
1
1
A0
0
1
0
1
Whole Word
Upper Byte from/to Odd Address
Lower Byte from/to Even Address
None
RD
32
O
READ: Read strobe indicates that the processor is performing a memory or I/O read cycle, depending
on the state of the M/IO or S2 pin. This signal is used to read devices which reside on the HS-80C86RH
local bus. RD is active LOW during T2, T3 and TW of any read cycle, and is guaranteed to remain HIGH
in T2 until the 80C86 local bus has floated.
This line is held at a high impedance logic one state during “hold acknowledge” or “grant sequence”.
READY
22
I
READY: is the acknowledgment from the addressed memory or I/O device that will complete the data
transfer. The RDY signal from memory or I/O is synchronized by the HS-82C85RH Clock Generator to
form READY. This signal is active HIGH. The HS-80C86RH READY input is not synchronized. Correct
operation is not guaranteed if the Setup and Hold Times are not met.
INTERRUPT REQUEST: is a level triggered input which is sampled during the last clock cycle of each
instruction to determine if the processor should enter into an interrupt acknowledge operation. If so, an
interrupt service routine is called via an interrupt vector lookup table located in system memory. INTR is
internally synchronized and can be internally masked by software resetting the interrupt enable bit. This
signal is active HIGH.
TEST: input is examined by the “Wait” instruction. If the TEST input is LOW execution continues,
otherwise the processor waits in an “Idle” state. This input is synchronized internally during each clock
cycle on the leading edge of CLK.
INTR
18
I
TEST
23
I
FN3035 Rev 0.00
August 2000
Page 4 of 30
HS-80C86RH
Pin Descriptions
SYMBOL
NMI
(Continued)
TYPE
I
DESCRIPTION
NON-MASKABLE INTERRUPT: is an edge triggered input which causes a type 2 interrupt. An interrupt
service routine is called via an interrupt vector lookup table located in system memory. NMI is not
maskable internally by software. A transition from LOW to HIGH initiates the interrupt at the end of the
current instruction. This input is internally synchronized.
RESET: causes the processor to immediately terminate its present activity. The signal must change from
LOW to HIGH and remain active HIGH for at least 4 CLK cycles. It restarts execution, as described in the
Instruction Set description, when RESET returns LOW. RESET is internally synchronized.
CLOCK: provides the basic timing for the processor and bus controller. It is asymmetric with a 33% duty
cycle to provide optimized internal timing.
VDD: +5V power supply pin. A 0.1F capacitor between pins 20 and 40 is recommended for decoupling.
GND: Ground. Note: both must be connected. A 0.1F capacitor between pins 1 and 20 is
recommended for decoupling.
I
MINIMUM/MAXIMUM: Indicates what mode the processor is to operate in. The two modes are discussed
in the following sections.
PIN
NUMBER
17
RESET
21
I
CLK
VDD
GND
MN/MX
19
40
1, 20
33
I
The following pin function descriptions are for the HS-80C86RH system in maximum mode (i.e., MN/MX = GND). Only the pin functions which are
unique to maximum mode are described below.
S0, S1, S2
26-28
O
STATUS: is active during T4, T1 and T2 and is returned to the passive state (1,1,1) during T3 or during
TW when READY is HIGH. This status is used by the 82C88 Bus Controller to generate all memory and
I/O access control signals. Any change by S2, S1, or S0 during T4 is used to indicate the beginning of a
bus cycle, and the return to the passive state in T3 or TW is used to indicate the end of a bus cycle. These
status lines are encoded. These signals are held at a high impedance logic one state during “grant
sequence”.
S2
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
Interrupt Acknowledge
Read I/O Port
Write I/O Port
Halt
Code Access
Read Memory
Write Memory
Passive
FN3035 Rev 0.00
August 2000
Page 5 of 30
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