are precision 16-bit multiplying DACs, that provide four-quadrant
multiplication. Both parts accept both AC and DC reference voltages. The
SP7516
is available
for use in commercial and industrial temperature ranges, packaged in a 24-pin SOIC. The
HS3160
is available in commercial and military temperature ranges, packaged in a 22-pin
side-brazed DIP.
V
REF
Force
V
REF
Sense
GND
V
DD
23
22
2
3
1
I
OUT
2 Sense
I
OUT
2 Force
I
OUT
1
4
21
SP7516
5
6
7
8
BIT4
20
BIT16
(LSB)
24
R
FEEDBACK
BIT1 BIT2 BIT3
(MSB)
Switches shown in high state.
V
REF
21
2
I
OUT
2
GND
V
DD
3
1
20
I
OUT
1
HS3160
4
5
6
7
BIT4
19
BIT16
(LSB)
22
R
FEEDBACK
BIT1 BIT2 BIT3
(MSB)
Switches shown in high state.
Corporation
127
SIGNAL PROCESSING EXCELLENCE
SPECIFICATIONS
(Typical @ 25°C, nominal power supply, V
REF
= +10V, unipolar unless otherwise noted)
PARAMETER
DIGITAL INPUT
Resolution
2–Quad, Unipolar Coding
4–Quad, Bipolar Coding
Logic Compatibility
Input Current
REFERENCE INPUT
Voltage Range
Input Impedance
ANALOG OUTPUT
Scale Factor
Scale Factor Accuracy
Output Leakage
Output Capacitance
C
OUT
1, all inputs high
C
OUT
1, all inputs low
C
OUT
2, all inputs high
C
OUT
2, all inputs low
STATIC PERFORMANCE
Integral Linearity
SP7516KN/BN, HS3160–4
SP7516JN/AN, HS3160–3
Differential Linearity
SP7516KN/BN, HS3160–4
SP7516JN/AN, HS3160–3
Monotonicity
SP7516KN/BN, HS3160–4
SP7516JN/AN, HS3160–3
STABILITY
Scale Factor
Integral Linearity
Differential Linearity
Monotonicity Temp. Range
SP7516JN/KN, HS3160C
SP7516AN/BN
HS3160B–_
DYNAMIC PERFORMANCE
Digital Small Signal Settling
Digital Full Scale Settling
Reference Feedthrough Error
@ 1kHz
@ 10kHz
Reference Input Bandwidth
POWER SUPPLY (V
DD
)
Operating Voltage
Voltage Range
Current
Rejection Ratio
MIN.
16
TYP.
MAX.
UNITS
Bits
CONDITIONS
Binary
Offset Binary
CMOS, TTL
±1
±25
9.75
225
±1
10
µA
V
KOhms
µA/V
REF
%
nA
pF
pF
pF
pF
Note 1
Note 2
3.25
75
Note 3
Note 4
100
50
50
100
±0.003
±0.006
±0.003
±0.006
±0.006
±0.012
±0.006
±0.012
Note 5
% FSR
% FSR
Note 6
%FSR
% FSR
Guaranteed to 14 bits
Guaranteed to 13 bits
(T
MIN
to T
MAX
)
Note 7 and 8
4
0.5
0.5
0
–40
–55
1.0
2.0
200
2
1
+15
±5%
+8
0.005
1.0
1.0
+70
+85
+125
ppm FSR/°C
ppm FSR/°C
ppm FSR/°C
°C
°C
°C
µS
µS
µV
mV
MHz
V
V
mA
%/%
(V
REF
= 20Vpp)
+18
2.0
Note 9
128
Corporation
SIGNAL PROCESSING EXCELLENCE
SPECIFICATIONS
(continued)
(Typical @ 25°C, nominal power supply, V
REF
= +10V, unipolar unless otherwise noted)
PARAMETER
MIN.
TYP.
MAX.
ENVIRONMENTAL AND MECHANICAL
Operating Temperature
SP7516JN/KN
0
+70
SP7516AN/BN
–40
+85
HS3160–C
0
+70
HS3160–B
–55
+125
HS3160–B/883
–55
+125
Storage Temperature
–65
+150
Package
SP7516_N
24-pin SOIC
HS3160
22–pin Side–Brazed DIP
UNITS
CONDITIONS
°C
°C
°C
°C
°C
°C
Notes:
1.
Digital input voltage must not exceed supply voltage or go below –0.5V ; “0” <0.8V; 2.4V < “1”
≤V
DD.
2.
AC or DC; use R6758–1 for fixed reference applications
3.
Using the internal feedback resistor and an external op amp. The Scale Factor can be adjusted externally by variable resistors in series with the
reference input and/or in series to the internal feedback resistor. Please refer to the Applications Information section.
4.
At 25°C; the output leakage current will create an offset voltage at the external op amps output. It doubles every 10°C temperature increase.
5.
Integral Linearity is measured as the arithmetic mean value of the magnitudes of the greatest positive deviation and the greatest negative deviation from
the theoretical value for any given input combination.
6.
Differential Linearity is the deviation of an output step form the theoretical value of 1LSB for any two adjacent digital input codes.
7.
At 25°C, the output leakage current will create an offset voltage output. It doubles every 10°C temperature increase.
8.
Using the internal feedback resistor and an external op amp.
9.
Use series 470ohm resistor to limit startup current.
CHARACTERISTIC CURVES
(Typical @ + 25°C, V
DD
= + 15VDC, V
REF
= + 10VDC, unless otherwise noted.)
INTEGRAL LINEARITY ERROR - %
0.048
50
0.024
LINEARITY ERROR - PPM
40
30
2 LSB
0.012
0.006
0.003
0.01
0.1
V REF -VOLTS
1
10
20
1 LSB
10
1/2 LSB @ 16 BITS
Integral Linearity Error vs. Reference Voltage
0.048%
0
0
10
20
30
VOS-mV
40
50
LINEARITY - %
0.024%
Additional Linearity Error vs. Output-Amplifier
Offset-Voltage (V
REF
= + 10V)
0.012%
0.01
0.006%
0.003%
4
6
8
10
12
14
16
18
0.008
V DD -VOLTS
Linearity vs. Supply Voltage
2.5
GAIN CHANGE - %
0.006
0.004
2.0
I DD -mA
0.002
1.5
0
1.0
4
6
8
10
12
14
16
18
10
VDD -VOLTS
4
6
8
10
12
14
16
18
VDD -VOLTS
Gain Change vs. Supply Voltage
Power Supply Current vs. Voltage
Corporation
129
SIGNAL PROCESSING EXCELLENCE
PIN ASSIGNMENTS
HS3160 22–PIN
Pin 1 – IO
1
– Current Output 1.
Pin 2 – IO
2
– Current Output 2.
Pin 3 – GND – Ground.
Pin 4 – DB
15
– MSB, Data Bit 1.
Pin 5 – DB
14
– Data Bit 2.
Pin 6 – DB
13
– Data Bit 3.
Pin 7 – DB
12
– Data Bit 4.
Pin 8 – DB
11
– Data Bit 5.
Pin 9 – DB
10
– Data Bit 6.
Pin 10 – DB
9
– Data Bit 7.
Pin 11 – DB
8
– Data Bit 8.
Pin 12 – DB
7
– Data Bit 9.
Pin 13 – DB
6
– Data Bit 10.
Pin 14 – DB
5
– Data Bit 11.
Pin 15 – DB
4
– Data Bit 12.
Pin 16 – DB
3
– Data Bit 13.
Pin 17 – DB
2
– Data Bit 14.
Pin 18 – DB
1
– Data Bit 15.
Pin 19 – DB
0
– LSB, Data Bit 16.
Pin 20 – V
DD
– Positive Supply Voltage.
Pin 21 – V
REF
– Reference Voltage Input.
Pin 22 – R
FB
– Feedback Resistor.
SP7516 24–PIN
Pin 1 – IO
1
– Current Output 1.
Pin 2 – IO
2
Sense – Current Output 2.
Pin 3 – IO
3
Force – Current Output 3.
Pin 4 – GND – Ground.
Pin 5 – DB
15
– MSB, Data Bit 1.
Pin 6 – DB
14
– Data Bit 2.
Pin 7 – DB
13
– Data Bit 3.
Pin 8 – DB
12
– Data Bit 4.
Pin 9 – DB
11
– Data Bit 5.
Pin 10 – DB
10
– Data Bit 6.
Pin 11 – DB
9
– Data Bit 7.
Pin 12 – DB
8
– Data Bit 8.
Pin 13 – DB
7
– Data Bit 9.
Pin 14 – DB
6
– Data Bit 10.
130
Pin 15 – DB
5
– Data Bit 11.
Pin 16 – DB
4
– Data Bit 12.
Pin 17 – DB
3
– Data Bit 13.
Pin 18 – DB
2
– Data Bit 14.
Pin 19 – DB
1
– Data Bit 15.
Pin 20 – DB
0
– LSB, Data Bit 16.
Pin 21 – V
DD
– Positive Supply Voltage.
Pin 22 – V
REF
Sense – Reference Voltage Input.
Pin 23 – V
REF
Force – Reference Voltage Input.
Pin 24 – R
FB
– Feedback Resistor.
FEATURES…
The
SP7516
and
HS3160
are precision 16-bit multi-
plying DACs. The DACs are implemented as a one-
chip CMOS circuit with a resistor ladder network.
Three output lines are provided on the DACs to allow
unipolar and bipolar output connection with a mini-
mum of external components. The feedback resistor
is internal. The resistor ladder network termination is
externally available, thus eliminating an external re-
sistor for the 1 LSB offset in bipolar mode.
The
SP7516
is available for use in commercial and
industrial temperature ranges, packaged in a 24-pin
SOIC. The
HS3160
is available in commercial
and military temperature ranges, packaged in a
24–pin side–brazed DIP. For product processed
and screened to the requirements of MIL–M–
38510 and MIL–STD–883C, please consult the
factory (HS3160B only).
PRINCIPLES OF OPERATION
The
SP7516/HS3160
achieve high accuracy by using
a decoded or segmented DAC scheme to implement
this function. The following is a brief description of
this approach.
Cf
Rf
VREF
Ri
CO
Rp
C
–
+
EO
Figure 1. SP7516/HS3160 Equivalent Output Circuit
Corporation
SIGNAL PROCESSING EXCELLENCE
2
- 1
(MSB)
0
0
1
1
2
-2
Output
0
1/4 Full-Scale
1/2 Full-Scale
3/4 Full-Scale
V REF
400Ω
470Ω
V DD
200Ω
RFEEDBACK
I O1
R OS
-
A
+
V OUT
0
1
0
1
Table 1. Contribution of the two MSB's
DIGITAL
INPUTS
SP7516
HS3160
I O2
The most common technique for building a D/A
converter of n bits is to use n switches to turn n current
or voltage sources on or off. The n switches and n
sources are designed so that each switch or bit contrib-
utes twice as much to the D/A converter’s output as the
preceding bit. This technique is commonly known as
binary weighting and allows an n-bit converter to
generate 2
n
output levels by turning on the proper
combination of bits.
In such a binary-weighted converter, the switch
with the smallest contribution (the LSB) accounts
for only 2
-n
of the converter’s full-scale value.
Similarly, the switch with the largest contribution
(the MSB) accounts for 2
-1
or half of the converter’s
full-scale output. Thus it is easy to see that a given
percent change in the MSB will have a greater
effect on the converter’s output than would a
similar percent change in the LSB. For example, a
1% change in the LSB of a 10 bit converter would
only affect the output by 0.001% of full-scale. A
1% change in the MSB of the same converter
would affect the output by 0.5% of FSR.
In order to overcome the problem which results from
the large weighting of the MSB, the two MSB’s can
be decoded to three equally weighted sources.
Table
1
shows that all combinations of the two MSB’s of a
converter result in four output levels. So by replacing
the two MSB’s with three bits equally weighted at 1/
4 full-scale and decoding the two MSB digital inputs
into three lines which drive the equally weighted bits,
GND
Figure 2. Unipolar Operation
the same functional performance can be obtained.
Thus by replacing the two MSB switches of a conven-
tional converter with three switches properly de-
coded, the contribution of any switch is reduced from
1/2 to 1/4. This reduction in sensitivity also reduces the
accuracy required of any switch for a given overall
converter accuracy.
With the decoded converter described above, a 1%
change in any of the converter’s switches will affect
the output by no more than 0.25% of full-scale as
compared to 0.5% for a conventional converter. In
other words the conventional D/A converter can be
made less sensitive to the quality of its individual bits
by decoding.
In the
SP7516/HS3160
the first four MSB’s are
decoded into 16 levels which drive 15 equally weighted
current sources. The sensitivity of each switch on the
output is reduced by a factor of 8. Each of the 15
sources contributes 6.25% output change rather than
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