ABSOLUTE MAXIMUM RATINGS
V
CC
to Digital Common .................................................. 0 to +16.5V
V
LOGIC
to Digital Common ................................................... 0 to +7V
Analog Common to Digital Common .........................................
±1V
Control Inputs to Digital Common ................. –0.5V to V
LOGIC
+0.5V
(CE, CS, A
0
, 12/8, R/C)
Analog Inputs to Analog Common ......................................
±16.5V
(REF IN, BIP OFF, 10V
IN
)
20V
IN
to Analog Common ........................................................
±24V
REF OUT ............................................... Indefinite short to common
Momentary short to V
CC
Power Dissipation ............................................................. 1000mW
Lead Temperature, Soldering ................................... 300˚C, 10Sec
ΘJ/C
................................................................................... 45˚C/W
MTBF–25˚C Ground Base ................................ 2.915 million hours
MTBF–125˚C Missile Launch ...................... 10.16 thousand hours
•
CAUTION:
ESD (ElectroStatic Discharge) sensitive
device. Permanent damage may occur on
unconnected devices subject to high energy
electrostatic fields. Unused devices must be
stored in conductive foam or shunts.
Personnel should be properly grounded prior
to handling this device. The protective foam
should be discharged to the destination
socket before devices are removed.
Inputs exceeding +30% or –30% of FS will cause erratic performance.
SPECIFICATIONS
(Typical @ 25°C with V
CC
= +15V, V
EE
= 0V, V
LOGIC
= +5V unless otherwise noted)
PARAMETER
MIN.
TYP.
MAX.
UNIT
CONDITIONS
RESOLUTION
All models
12
Bits
ANALOG INPUTS
Input Ranges
Bipolar
±5, ±10
V
Unipolar
0 to +10, 0 to +20
V
Input Impedance
10 Volt Input
3.75
6.25
KΩ
20 Volt Input
15
25
KΩ
DIGITAL INPUTS
Logic Inputs CE, CS R/C, A
O
, 12/8
Logic 1
+2.4
+5.5
V
Logic 0
–0.3
+0.8
V
Current
±0.1
±50
µA
0V to +5.5V Input
Capacitance
5
pF
12/8 Control Input
Hardwire to V
LOGIC
or DIGITAL COMMON (SP574A only)
DIGITAL OUTPUTS
Logic Outputs DB
11
–DB
0
, STS
Logic 1
+2.4
V
I
SOURCE
≤
500µA
Logic 0
+0.4
V
I
SINK
≤
1.6mA
Leakage (High Z State)
±40
µA
Data bits only
Capacitance
5
pF
Parallel Data Output Codes
Unipolar
Positive true binary
Bipolar
Positive true offset binary
REFERENCE
Internal
10.00
±0.1
V
Output Current
2
mA
Note 1
CONVERSION TIME
HS574A
12–Bit Conversion
13
25
µs
8–Bit Conversion
10
19
µs
SP674A
12–Bit Conversion
9
15
µs
8–Bit Conversion
6
11.25
µs
4
FEATURES…
The
HS574A/SP674A
feature standard bipolar
and unipolar input ranges of 10V and 20V. Input
ranges are controlled by a bipolar offset pin and
laser-trimmed for specified linearity, gain and
offset accuracy. Power requirements are +5V
and +12V to +15V with a maximum dissipation
of 150mW at the specified voltages. Conversion
times of 8µs, 10µs, 15µs and 25µs are available,
as are units with 10, 25 or 50ppm/°C temperature
coefficients for flexible matching to specific
application requirements.
The
HS574A/SP674A
are available in six prod-
uct grades for each conversion time. The –J, –K
and –L models are specified over 0˚C to + 70˚C
commercial temperature range; the –S, –T and –
U models are specified over the –55˚C to +125˚C
military temperature range. Processing in accor-
dance with MIL–STD–883C is also available.
The HS574A/SP674A are packaged in a 28–pin
CerDIP. Please consult the factory for other
packaging options.
CIRCUIT OPERATION…
The
HS574A/SP674A
are complete 12–bit ana-
log-to-digital converters with integral voltage
reference, comparator, successive–approxima-
tion register (SAR), sample–and–hold, clock,
output buffers and control circuitry. The high
level of integration of the
HS574A/SP674A
means they require few external components.
When the control section of the
HS574A/SP674A
initiates a conversion command, the clock is
enabled and the successive–approximation reg-
ister is reset to all zeros. Once the conversion
cycle begins, it can not be stopped or re–started
and data is not available from the output buffers.
The SAR, timed by the clock, sequences through
the conversion cycle and returns an end–of–
convert flag to the control section of the ADC.
The clock is then disabled by the control section,
the output status goes low, and the control sec-
tion is enabled to allow the data to be read by
external command.
The internal
HS574A/SP674A
12–bit CDAC is
sequenced by the SAR starting from the MSB to
the LSB at the beginning of the conversion cycle
to provide an output voltage from the CDAC that
is equal to the input signal voltage (which is
divided by the input voltage divider network).
The comparator determines whether the addition
of each successively–weighted bit voltage causes
the CDAC output voltage summation to be greater
or less than the input voltage; if the sum is less,
the bit is left on; if more, the bit is turned off.
After testing all the bits, the SAR contains a 12–
bit binary code which accurately represents the
input signal to within
±
1
⁄
2
LSB.
The internal reference provides the voltage refer-
ence to the CDAC with excellent stability over
temperature and time. The reference is trimmed
to 10.00 Volts
±1%
and can supply up to 2mA to
an external load in addition to that required to
drive the reference input resistor (1mA) and
offset resistor (1mA) when operating with
±15V
supplies. If the
HS574A/SP674A
is used with
±12V
supplies, or if external current must be
supplied over the full temperature range, an
external buffer amplifier is recommended. Any
external load on the
HS574A/SP674A
reference
must remain constant during conversion.
The sample and hold is a default function by
virtue of the CDAC architecture. Therefore the
majority of the S/H specifications are included
within the A/D specifications.
Sample–and–Hold Function
Although there is no sample-and-hold circuit in
the classical sense, the sampling nature of the
capacitive DAC makes the
HS574A/SP674A
appear to have a built in sample and hold. This
sample and hold action substantially increases
the usefulness of the
HS574A/SP674A
over that
of similar competing devices.
Note that even though the user may use an
external sample and hold for very high fre-
quency inputs, the internal sample and hold still
provides a very useful isolation function. Once
the internal sample is taken by the CDAC capaci-
tance, the input of the
HS574A/SP674A
is dis-
connected from the input. This prevents tran-
sients occurring during conversion from being
inflicted upon the attached buffer. All other 574/
674 circuits will cause a transient load current on
7
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
