HANBit
HSD32M32M4V
Synchronous DRAM Module 128Mbyte ( 32M x 32-Bit ) 72-Pin SIMM based on
32Mx8, 4Banks, 8K Ref., 3.3V
Part No. HSD32M32M4V
GENERAL DESCRIPTION
The HSD32M32M4V is a 32M x 32 bit Synchronous Dynamic RAM high density memory module. The module consists
of four CMOS 8M x 8 bit with 4banks Synchronous DRAMs in TSOP-II packages mounted on a 72-pin, FR-4-printed circuit
board. Two 0.01uF decoupling capacitor is mounted on the printed circuit board in parallel for each SDRAM. The
HSD32M32M4V is a SIMM designed. Synchronous design allows precise cycle control with the use of system clock. I/O
transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same
device to be useful for a variety of high bandwidth, high performance memory system applications All module components
may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.
FEATURES
•
Part Identification
HSD32M32M4V-13/F13 :133MHz ( CL=3)
HSD32M32M4V-12/F12: 125MHz (CL=3)
HSD32M32M4V-10/F10: 100MHz (CL=2)
HSD32M32M4V-10L/F10L: 100MHz
F means Auto & Self refresh with Low
–
Power (3.3V)
•
Burst mode operation
•
Auto & self refresh capability (8192 Cycles/64ms)
•
LVTTL compatible inputs and outputs
•
Single 3.3V
±0.3V
power supply
•
MRS cycle with address key programs
- Latency (Access from column address)
- Burst length (1, 2, 4, 8 & Full page)
- Data scramble (Sequential & Interleave)
•
All inputs are sampled at the positive going edge
of the system clock
•
FR4-PCB design
•
72-Pin SIMM Package
•
The used device is 8Mx8bitx4Bank SRAM
•
Pin assignment is compatible with
- HSD8M32M4V
- HSD16M32M4V
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PIN ASSIGNMENT
SYMBOL
Vss
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM0
Vcc
NC
A0
A1
A2
A3
A4
Vss
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
PIN
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
SYMBOL
DQ14
DQ15
DQM1
NC
/WE
/CAS
Vcc
/RAS
/CS0
NC
NC
CLK0
CKE0
Vss
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQM2
Vcc
PIN
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
SYMBOL
A5
A6
A7
A8
A9
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQM3
NC
A10/AP
A11
A12
Vcc
BA0
BA1
NC
NC
Vss
72-PIN SIMM TOP VIEW
URL:www.hbe.co.kr
REV.1.0 (August.2002)
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HANBit Electronics Co.,Ltd
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FUNCTIONAL BLOCK DIAGRAM
HSD32M32M4V
DQ0-31
CKE0
/CAS
/RAS
/CE1
CKE
CAS
RAS
CE
WE
A0-A12
CLK
CLK0
U1
DQ0-7
DQM0
BA0-1
DQM0
CKE
CAS
RAS
CE
WE
A0-A12
CLK
CLK0
U2
DQ8-15
DQM0
BA0-1
DQM1
CKE
CAS
RAS
CE
WE
A0-A12
CLK
CLK0
U3
DQ16-23
DQM0
BA0-1
DQM2
CKE
CAS
RAS
CE
WE
A0-A12
CLK
CLK0
U4
DQ24-31
DQM0
BA0-1
DQM3
/WE
A0 - A12
BA0-1
Vcc
Two 0.01uF Capacitor
per each SDRAM
Vss
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REV.1.0 (August.2002)
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PIN FUNCTION DESCRIPTION
Pin
CLK
/CE
Name
System clock
Chip enable
Input Function
HSD32M32M4V
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
CKE
Clock enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+tSS prior to valid command.
A0 ~ A12
Address
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA12, Column address : CA0 ~ CA9
BA0 ~ BA1
Bank select address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
/RAS
Row address strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
/CAS
Column
strobe
address
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
/WE
Write enable
DQM0 ~ 3
Data
mask
input/output
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
DQ0 ~ 31
VDD/VSS
Data input/output
Power
supply/ground
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Voltage on Any Pin Relative to Vss
Voltage on Vcc Supply Relative to Vss
Power Dissipation
Storage Temperature
SYMBOL
V
IN ,OUT
Vcc
P
D
T
STG
RATING
-1V to 4.6V
-1V to 4.6V
4W
-55oC to 150oC
Short Circuit Output Current
I
OS
50mA
Notes :
Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be
restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
URL:www.hbe.co.kr
REV.1.0 (August.2002)
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HANBit Electronics Co.,Ltd
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HSD32M32M4V
DC OPERATING CONDITIONS
(Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C) )
PARAMETER
Supply Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
SYMBOL
Vcc
V
IH
V
IL
V
OH
V
OL
MIN
3.0
2.0
-0.3
2.4
-
TYP.
3.3
3.0
0
-
-
MAX
3.6
Vcc+0.3
0.8
-
0.4
UNIT
V
V
V
V
V
1
2
I
OH
= -2mA
I
OL
= 2mA
3
NOTE
Input leakage current
I
LI
-10
-
10
uA
Notes :
1. V
IH
(max) = 5.6V AC. The overshoot voltage duration is
≤
3ns.
2. V
IL
(min) = -2.0V AC. The undershoot voltage duration is
≤
3ns.
3. Any input 0V
≤
V
IN
≤
V
DDQ
.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
(VCC = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V
±
200 mV)
DESCRIPTION
Address(A0~A12, BA0~BA1)
/RAS, /CAS, /WE
CKE(CKE0)
Clock (CLK0)
/CE (/CE1)
DQM (DQM0 ~ DQM3)
DQ (DQ0 ~ DQ32)
SYMBOL
C
ADD
C
IN
C
CKE
C
CLK
C
CS
C
DQM
C
OUT
MIN
15
15
15
7.5
15
6.5
7
MAX
25
25
25
9
25
7.5
8.5
UNITS
pF
pF
pF
pF
pF
pF
pF
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
TEST
PARAMETER
SYMBOL
CONDITION
Burst length = 1
Operating current
(One bank active)
I
CC1
t
RC
≥
t
RC
(min)
I
O
= 0mA
I
CC2
P
CKE
≤
V
IL
(max)
t
CC
=10ns
CKE & CLK
≤
V
IL
(max)
t
CC
=∞
8
mA
8
mA
480
480
440
440
mA
1
-A
-8
-H
-L
VERSION
UNIT
NOTE
Precharge standby current in
power-down mode
I
CC2
PS
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REV.1.0 (August.2002)
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HANBit Electronics Co.,Ltd
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CKE
≥
V
IH
(min)
I
CC2
N
Precharge standby current in
one time during 20ns
non power-down mode
I
CC2
NS
CKE
≥
V
IH
(min)
CLK
≤
V
IL
(max),
t
CC
=∞
CS*
≥
V
IH
(min),
t
CC
=10ns
HSD32M32M4V
64
mA
Input signals are changed
56
Input signals are stable
Active
standby
current
in
I
CC3
P
I
CC3
PS
CKE
≤
V
IL
(max), t
CC
=10ns
CKE&CLK
≤
V
IL
(max)
t
CC
=∞
CKE≥V
IH
(min),
I
CC3
N
CS*≥V
IH
(min),
t
CC
=10ns
120
mA
24
mA
24
power-down mode
Active standby current in
non power-down mode
(One bank active)
Input signals are changed
one time during 20ns
CKE≥VIH(min)
I
CC3
NS
CLK
≤VIL(max),
t
CC
=∞
100
Input signals are stable
I
O
= 0 mA
Operating current
(Burst mode)
I
CC4
Page burst
560
4Banks Activated
t
CCD
= 2CLKs
Refresh current
Self refresh current
I
CC5
I
CC6
t
RC
≥
t
RC
(min)
CKE
≤
0.2V
840
840
20
8
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noticed, input swing level is CMOS(V
IH
/V
IL
=V
DDQ
/V
SSQ
).
800
800
mA
mA
mA
2
G
F
560
460
460
mA
1
AC OPERATING TEST CONDITIONS
(vcc = 3.3V
±
0.3V, TA = 0 to 70°C)
PARAMETER
AC Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
2.4/0.4
1.4
tr/tf = 1/1
1.4
See Fig. 2
UNIT
V
V
ns
V
URL:www.hbe.co.kr
REV.1.0 (August.2002)
-5-
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