HANBit
HSD8M72D9A
Synchronous DRAM Module 64Mbyte (8Mx72bit),DIMM with ECC
based on 8Mx8, 4Banks, 4K Ref., 3.3V
Part No. HSD8M72D9A
GENERAL DESCRIPTION
The HSD8M72D9A is a 8M x 72 bit Synchronous Dynamic RAM high density memory module. The module consists of
nine
CMOS 2M x 8 bit with 4banks Synchronous DRAMs in TSOP-II 400mil packages on a 168-pin glass-epoxy
substrate. Two 0.33uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The
HSD8M72D9A is a DIMM(Dual in line Memory Module) and is intended for mounting into 168-pin edge connector sockets.
Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high
bandwidth, high performance memory system applications All module components may be powered from a single 3.3V DC
power supply and all inputs and outputs are LVTTL-compatible.
FEATURES
•
Part Identification
HSD8M72D9A-F/10H : 100MHz (CL=2&3)
HSD8M72D9A-F/10L : 100MHz (CL=3)
HSD8M72D9A-F/10 : 100MHz (CL=2)
HSD8M72D9A-F/13 : 133MHz (CL=3)
HSD8M72D9A-F/13H : 133MHz (CL=2)
F means Auto & Self refresh with Low-Power (3.3V)
•
Burst mode operation
•
Auto & self refresh capability (4096 Cycles/64ms)
•
LVTTL compatible inputs and outputs
•
Single 3.3V
±0.3V
power supply
•
MRS cycle with address key programs
- Latency (Access from column address)
- Burst length (1, 2, 4, 8 & Full page)
- Data scramble (Sequential & Interleave)
•
All inputs are sampled at the positive going edge of the system clock
•
The used device is 2M x 8bit x 4Banks SDRAM
URL: www.hbe.co.kr
REV 1.0 (August.2002)
1
HANBit Electronics Co.,Ltd.
HANBit
PIN ASSIGNMENT
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Symbol
Vss
DQ0
DQ1
DQ2
DQ3
Vcc
DQ4
DQ5
DQ6
DQ7
DQ8
Vss
DQ9
DQ10
DQ11
DQ12
DQ13
Vcc
DQ14
DQ15
CB0
CB1
Vss
NC
NC
Vcc
/WE
DQM0
PIN
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Symbol
DQM1
/CS0
NC
Vss
A0
A2
A4
A6
A8
A10
BA1
Vcc
Vcc
CLK0
Vss
NC
/CS2
DQM2
DQM3
NC
Vcc
NC
NC
CB2
CB3
Vss
DQ1C6
DQ17
PIN
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Symbol
DQ18
DQ19
Vcc
DQ20
NC
NC
NC
Vss
DQ21
DQ22
DQ23
Vss
DQ24
DQ25
DQ26
DQ27
Vcc
DQ28
DQ29
DQ30
DQ31
Vss
CLK2
NC
WP
SDA
SCL
Vcc
PIN
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
Symbol
Vss
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
DQ40
Vss
DQ41
DQ42
DQ43
DQ44
DQ45
Vcc
DQ46
DQ47
CB4
CB5
Vss
NC
NC
Vcc
/CAS
DQM4
PIN
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
HSD8M72D9A
Symbol
DQM5
NC
/RAS
Vss
A1
A3
A5
A7
A9
BA0
A11
Vcc
CLK1
A12
Vss
CKE0
NC
DQM6
DQM7
NC
Vcc
NC
NC
CB6
CB7
Vss
DQ48
DQ49
PIN
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Symbol
DQ50
DQ51
Vcc
DQ52
NC
NC
NC
Vss
DQ53
DQ54
DQ55
Vss
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
DQ61
DQ62
DQ63
Vss
CLK3
NC
SA0
SA1
SA2
Vcc
URL: www.hbe.co.kr
REV 1.0 (August.2002)
2
HANBit Electronics Co.,Ltd.
HANBit
FUNCTIONAL BLOCK DIAGRAM
DQ0-63
CB0-7
CKE0
/CA
CKE
CAS
RAS
CE
WE
A0-A11
HSD8M72D9A
U1
CLK
DQ0-7
DQM0
BA0-1
CLKA
DQM0
/RAS
/CS0
CKE
CAS
RAS
U6
WE
A0-A11
CLK
DQ16-23
DQM2
BA0-1
CLK
DQ32-39
DQM4
CLKB
DQM2
/CS
CE
CKE
CAS
RAS
CE
CKE
CAS
RAS
CE
CKE
CAS
RAS
CE
U2
WE
A0-A11
DQM4
BA0-1
CLK
DQ48-55
DQM6
BA0-1
CLK
CB0-7
DQM1
BA0-1
U7
WE
A0-A11
DQM6
U5
WE
A0-A11
DQM1
CKE
CAS
RAS
CE
CKE
CAS
RAS
CE
CKE
CAS
RAS
CE
WE
WE
WE
U3
A0-A11
CLK
DQ8-15
DQM1
BA0-1
CLK
DQ24-31
DQM3
BA0-1
CLK
DQ40-47
DQM5
DQM1
U8
A0-A11
DQM3
U4
A0-A11
DQM5
BA0-1
CKE
CAS
RAS
CE
WE
U9
A0-A11
CLK
DQ56-63
DQM7
BA0-1
DQM7
Vcc
Vss
/WE
A0 - A11
BA0-1
URL: www.hbe.co.kr
REV 1.0 (August.2002)
3
Two 0.1uF Capacitors
per each SDRAM
HANBit Electronics Co.,Ltd.
HANBit
PIN FUNCTION DESCRIPTION
PIN
CLK
/CE
NAME
System clock
Chip enable
INPUT FUNCTION
HSD8M72D9A
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
CKE
Clock enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+tSS prior to valid command.
A0 ~ A11
Address
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11, Column address : CA0 ~ CA8
BA0 ~ BA1
Bank select address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
/RAS
Row address strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
/CAS
Column address
strobe
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
/WE
Write enable
DQM0 ~ 7
Data input/output
mask
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
DQ0 ~ 63
VDD/VSS
Data input/output
Power
supply/ground
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Voltage on Any Pin Relative to Vss
Voltage on Vcc Supply Relative to Vss
Power Dissipation
Storage Temperature
SYMBOL
V
IN ,OUT
Vcc
P
D
T
STG
RATING
-1V to 4.6V
-1V to 4.6V
9W
-55oC to 150oC
Short Circuit Output Current
I
OS
450mA
Notes:
Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be
restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
URL: www.hbe.co.kr
REV 1.0 (August.2002)
4
HANBit Electronics Co.,Ltd.
HANBit
DC OPERATING CONDITIONS
(Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70° C) )
PARAMETER
Supply Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
SYMBOL
Vcc
V
IH
V
IL
V
OH
V
OL
MIN
3.0
2.0
-0.3
2.4
-
TYP.
3.3
3.0
0
-
-
MAX
3.6
Vcc+0.3
0.8
-
0.4
HSD8M72D9A
UNIT
V
V
V
V
V
NOTE
1
2
I
OH
= -2mA
I
OL
= 2mA
3
Input leakage current
I
LI
-10
-
10
uA
Notes :
1. V
IH
(max) = 5.6V AC. The overshoot voltage duration is
≤
3ns.
2. V
IL
(min) = -2.0V AC. The undershoot voltage duration is
≤
3ns.
3. Any input 0V
≤
V
IN
≤
V
DDQ
.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
(VCC = 3.3V, TA = 23° C, f = 1MHz, VREF =1.4V
±
200 mV)
DESCRIPTION
Clock
/RAS, /CAS,/WE,/CS, CKE, DQM
Address
DQ (DQ0 ~ DQ7)
SYMBOL
C
CLK
C
IN
C
ADD
C
OUT
MIN
2.5
2.5
2.5
4.0
MAX
4.0
5.0
5.0
6.5
UNITS
pF
pF
pF
pF
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70° C)
SYMB
PARAMETER
OL
Operating current
(One bank active)
Precharge standby current
In power-down mode
I
CC1
I
CC2
P
I
CC2
PS
CONDITION
Burst length = 1
t
RC
≥
t
RC
(min) I
O
= 0mA
CKE
≤
V
IL
(max), t
CC
=10ns
CKE & CLK
≤
V
IL
(max)
t
CC
=∞
CKE
≥
V
IH
(min)
I
CC2
N
Precharge standby current
one time during 20ns
In non power-down mode
I
CC2
NS
CKE
≥
V
IH
(min)
CLK
≤
V
IL
(max),
t
CC
=∞
6
mA
CS*
≥
V
IH
(min),
t
CC
=10ns
15
75
75
75
1
1
70
70
mA
mA
mA
1
13H
-13
-12
-10
-10L
TEST
VERSION
UNIT
NOTE
Input signals are changed
Input signals are stable
Active standby current in
URL: www.hbe.co.kr
REV 1.0 (August.2002)
I
CC3
P
CKE
≤
V
IL
(max), t
CC
=10ns
5
3
mA
HANBit Electronics Co.,Ltd.
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