(IC) is an off-line, high-power factor, buck-boost
controller targeted at general LED lighting products,
such as LED lamps and LED lighting fixtures with a
maximum power rating of about 15W.
Valley-switching buck-boost converters are preferred in
off-line applications since they reduce switching losses.
A typical solution is to pair a constant on-time control
scheme with valley switching to achieve both a
high-power factor and good efficiency. However, this
control scheme results in a higher total harmonic distor-
tion, and the actual value is dependent on the input and
output voltages. The HV98100/HV98101 uses a unique
control scheme to achieve a high-power factor and low
THD simultaneously under all line and load conditions,
while maximizing efficiency utilizing valley switching.
The average LED current is also controlled in a closed-
loop manner to achieve high LED accuracy.
Other unique features of the ICs are the bootstrap of
the IC supply voltage from the output, as well as the
unique valley-sensing scheme that allows the use of a
standard off-the-shelf inductor to minimize the overall
system cost.
Applications with low-output voltage
accommodated using a coupled inductor.
can
be
Applications
• LED Lamps
• LED Lighting Fixtures
Package Types
HV98100/HV98101
6-Lead SOT-23
IND 1
GND 2
COMP 3
6 GATE
5 PV
DD
4 CS
See
Table 3-1
for pin description.
2016 Microchip Technology Inc.
DS20005640A-page 1
HV98100/HV98101
Typical Application Circuit
D
HV
R
HV
P
VDD
M
BBT
GT
CS
C
REC
R
CS
HV98100/1
COMP
D
BBT
C
PVDD
R
PVDD
C
COMP
GND
IND
R
VD
L
BBT
V
AC
C
O
D
VD
D
PVDD
LED
Internal Block Diagram
OCP
I_VO
Gate
P
VDD
P
VDD
POR
Fault
Protection
FLT
I_VO
I_V O
DET _V AL
VDD
on
/VDD
of f
IND
IN
Reg
A
VDD
Valley_Det
Valley Detect
GATE
Gate
GT_ON
Startup
clock
RESET
f
sta rt
Monoshot
Gate
Monoshot
Vton_ref
Max F req
Clock
POR
S
R
Gate
Gate
P
VDD
GATE
STRT_UP
RES E T
V_TON
Q
Q FLT
OCP_REF
LEB
OCP
Gate
GT_R
REF
THD
control
GND
COMP
CS_REF
CS
POR
DS20005640A-page 2
2016 Microchip Technology Inc.
HV98100/HV98101
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
Supply Voltage PV
DD
to GND ..................................................................................................................... -0.3V to +20V
GATE to GND.................................................................................................................................-0.3V to (PV
DD
+0.5V)
CS, COMP, IND to GND............................................................................................................................... -0.3V to 4.5V
Operating Junction Temperature.............................................................................................................-40°C to +125°C
Storage Temperature ..............................................................................................................................-65°C to +150°C
Power Dissipation at +25°C for 6L-SOT-23 .........................................................................................................800 mW
ESD Protection on all pins (HBM) ..............................................................................................................................2 kV
ESD Protection on all pins (MM) ...............................................................................................................................175V
* Based on JEDEC JESD51 testing and reporting standards
†
Notice:
Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at those or any other conditions above those indicated in
the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended
periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
Electrical Specifications:
Unless otherwise specified, all specifications are for T
A
= T
J
= +25°C, PV
DD
= 12V. Boldface
specifications apply over the full temperature range T
A
= T
J
= -40°C to +125°C.
Parameter
Power Supply (PV
DD
)
PV
DD
Clamp Voltage
PV
DD,clamp
15.5
17
18.5
V
Current into PV
DD
= 4.0 mA;
C
GATE
= 500 pF;
f
sw
= 100 kHz;
GATE starts switching
GATE stops switching
Note 1
Measured at PV
DD
= 12V
after PV
DD
rises from 0V to
12V
C
GATE
= 500 pF;
f
sw
= 100 kHz; COMP = 3V;
I_IND
SINK
= 200
μA;
I_IND
SOURCE
= 250
μA
Note 2
Note 2
C
GATE
= 500 pF
C
GATE
= 500 pF
Note 2
Note 2
1V COMP
4V; Output
open
Note 1
1V COMP 4V;
Note 1
CCOMP = 150 pF
(Note
2)
Symbol
Min.
Typ.
Max.
Units
Conditions
V
DD
Start Voltage
V
DD
Stop Voltage
Current into clamp
Current drawn by IC before start
V
DD,ON
V
DD,OFF
I
DD,max
I
DD,Q
14.5
6.5
—
—
16
8
—
—
17.5
9.5
5
200
V
V
mA
μA
Current drawn by IC during operation
I
DD,OP
—
—
4.3
mA
Gate Driver
GATE Driver Sourcing Current
Gate Driver Sinking Current
Gate Rise Time (10%-90%)
Gate Fall Time (10%-90%)
Output Current Control
Internal Reference Voltage
OTA Offset Voltage
Open Loop DC Gain
Small Signal Transconductance
Gain Bandwidth Product
CS
REF
V
OFFSET
A
V
g
m
GBW
194
-7.5
55
160
0.16
204
—
—
230
0.24
214
7.5
—
300
—
mV
mV
dB
μA/V
MHz
I
SOURCE
I
SINK
T
RISE
T
FALL
0.3
0.6
—
—
—
—
—
—
—
—
45
23
A
A
ns
ns
2016 Microchip Technology Inc.
DS20005640A-page 3
HV98100/HV98101
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications:
Unless otherwise specified, all specifications are for T
A
= T
J
= +25°C, PV
DD
= 12V. Boldface
specifications apply over the full temperature range T
A
= T
J
= -40°C to +125°C.
Parameter
R
ON
of COMP Reset FET
Internal Clocks
Start-up Clock
Maximum Frequency Limit
Valley Detect
Current into IND pin
Voltage at IND pin
Comparator Delay Time
Control Circuit
Internal Timing Constant
Internal Voltage for Timing
GATE On-time
T
ON
6.11
T
ON
Protection
Over Voltage Protection Current
Threshold
Over Current Protection Reference
Over Current Protection Blanking Time
Detect time for Over Current Protection
Over Current Comparator Delay
Note 1:
2:
I
OVP
OCP
REF
T
BLNKOCP
T
DETOCP
OCP
DLY
350
2.2
150
150
—
450
2.35
—
—
50
550
2.5
250
250
100
μA
V
ns
ns
ns
Note 2
After TBLNKOCP (Note
2)
100 mV overdrive (Note
2)
GATE = LOW
6.7
7.05
μs
K
T
V
Tref
—
—
—
6.83
1.25
2
2.5
7.35
—
—
—
7.89
μs
V
V
μs
HV98100
HV98101
HV98100
Ext Clk = 50 kHz
COMP = 2V
HV98101
Ext CSlk = 50 kHz
COMP = 2V
I
IND
V
IND
T
delay
—
3.87
—
—
4.3
—
600
4.73
50
μA
V
ns
Note 2
I
IND
= 250
μA
Note 2
F
start
F
max
6.25
217
10
320
15
480
kHz
kHz
Note 1
Symbol
R
COMP
Min.
300
Typ.
400
Max.
500
Units
Conditions
Obtained by Design and Characterization; not 100% tested in production.
Design Guidance only.
TABLE 1-1:
TEMPERATURE SPECIFICATIONS
Symbol
T
A
T
J
JA
JC
Min.
-65
-40
—
—
Typ.
—
—
124
74
Max.
+150
+125
—
—
Units
°C
°C
°C/W
°C/W
Conditions
Parameter
Temperature Ranges
Storage Temperature
Operating Junction Temperature
Thermal Package Resistance
Thermal Resistance, 6L-SOT-23
DS20005640A-page 4
2016 Microchip Technology Inc.
HV98100/HV98101
2.0
Note:
TYPICAL OPERATING CURVES
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note:
Unless otherwise indicated, T
A
= T
J
= +25°C, PV
DD
= 12V. Boldface specifications apply over the full temperature
I use eZdsp F2812 to write a program that use CpuTimer0 interrupt. This interrupt consists of many call function.
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嵌入式系统
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