MX86251
1.Introduction
A graphics subsystem using the MX86251 and 3Dfx In-
teractive Voodoo Rush
TM
combines industry leading 3D
performance with the proven performance and compat-
ibility of an industry standard 2D Windows accelerator.
This union creates an extremely cost effective and un-
compromising multimedia solution. The MX86251 pro-
vides a PCI system interface and high performance VGA,
2D, and Video features in a low cost 2D chip while the
Voodoo Rush
TM
delivers 3D graphics processing power.
The MX86251 connects to Voodoo Rush
TM
through the
high performance 64-bit VR interface. The VR interface
supports the render/refresh operation of the 2D/3D en-
gines and the system control of the 3D devices. The
MX86251 supports not only the basic Double Buffer
Scheme, but also Triple and Quad buffer swap for super
smooth animation and 3D stereo glasses applications.
The STATUS signal provides 3D status to the PCI host
through the MX86251.
The MX86251 is based on proven MX86250 2D/Video
window accelerator technology, while adding many en-
hancements to the base functionality. All processing en-
gines on the chip are running on a faster clock, up to 75
MHz which means 600 MB/sec peak memory bandwidth.
Higher bandwidth means higher 2D performance and
higher frame rate Video. The Linear Frame Buffer write
cycle from the PCI bus is now executed in one clock cycle.
That is, the CPU now has much greater write bandwidth
into frame buffer memory. The on chip RAMDAC is en-
hanced to 160 MHz to enable many high resolution video
modes. Contrast and Brightness adjustments are added
to the Video Processor so that dark MPEG-1 videos will
look much better on the screen. ALL these features of
the MX86251 combines to make a powerful graphics
experience for multimedia.
1.1 Features
Interface to 3Dfx VOODOO RUSH
TM
3D graphic chipset
• Provide industry leading price / performance in 2D and
Video
• Enable the add-in of advanced 3Dfx Interactive
Voodoo Rush
TM
3D texture mapping and pixel
rendering engines
• 4MB frame buffer enables higher resolution 3D
graphics
• Double, Triple and Quad buffer swap
• Optimized LFB PCI write cycles with packing FIFO for
most efficient usage of frame buffer bandwidth
Very high bandwidth, up to 600 MB/sec
• Achieves single clock cycle EDO DRAM access in
Graphics Co-processor, Video Processor and Display
Processor
• Delivers 600 MB/sec bandwidth with -35 EDO DRAM
running at 75 MHz
• Provides 400 MB/sec memory bandwidth using lower
cost -50 EDO DRAM chips
High Performance 64-bit Graphics Co-processor
• High performance graphics engine with 64 bit wide data
path and memory data bus
• Uniformly accelerated graphics operations in all pixel
formats: 256 color, High color and True color
• Optimized graphics engine for BitBLTs, rectangle fill,
pattern fill, line draw, color expansion, text transfer,
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and clipping
Advanced 3 operand BitBLT ALU executes all 256
Raster Operations (ROPs)
On chip 8x8x32 pattern memory achieves highest
throughput in the most common BitBLT in Windows
-- the Pattern BLT
Deep on-chip Source and Destination FIFOs for
sustained burst cycles in BitBLTs
Double buffered Co-processor registers allow
concurrent processing with CPU
Built in hardware cursor
Arbitrary X-Stride for efficient offscreen memory
allocation
Motion Video Codec Acceleration
• Contrast brightness adjustment
• YUV/YCrCb conversion of industry standard YUV 4.2.2
formats
• Video window zoom in both X and Y direction with
arbitrary ratio
• Interpolation with Bi-linear filters in both Horizontal and
Vertical dimensions
• Color Key supports video overlay
• Video window is double buffered
• Video is always played in True Color
Media Port interface to MPEG decoder chips or Video
Capture front-end
• Glueless interface to VMI (Video Module Interface)
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MX86251
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connector for
hardware MPEG-2 decoder using plug-in daughter
card
Glueless interface to Phillips 7110 for live video input
Interlaced video can be captured either one field only
or converted to higher resolution non-interlaced frame
Built in FIFO and flexible decimator
High speed PCI local bus interface
• Support zero wait state PCI burst cycles for maximum
CPU write bandwidth
• Single clock cycle PCI write to frame buffer memory
• level command and data FIFO
Flexible Display Memory configuration
• 1, 2, or 4 MB display memory
• 256K x 4, 256K x 8, and 256K x 16 dual CAS or dual
WE DRAM
• Fast-page and EDO
Fully Integrated for lower system cost
• Integrated 24 bit True Color RAMDAC supports 160
MHz pixel rate and 256x18 look-up table with High
Color and True color bypass
• Dual integrated clock synthesizers
• VESA Display Data Channel (DDC-1/2AB) protocol
support
• Support I
2
C channel interface
• General purpose I/O pins
"Green PC" power management
• Support VESA DPMS (Display Power Management)
standard
• Built in advanced power management techniques such
as internal DAC power down mode and clock idle
modes
Complete Hardware compatibility
• Windows 95 Plug and Play compliant
• VGA hardware, register, and BIOS level 100%
compatible
• PCI revision 2.1 compatible
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MX86251
208PIN PQFP PACKAGE
XI
XO
AVDD
AGND
SCOMP
AGND
AVDD
VDDP
VDD
GND
PCICLK
PFXRSTL
PDEVSELS
PIRDYL
PTRDYL
PSTOPL
PFRAMEL
PAR
PCBE3L
GNDP
PCBE2L
PRESETL
PCBE1L
PCBE0L
PIDSEL
PMCK3DFX
PFXSWAP
VMIDTACKL
VMIHSEL3
PSTROBE
P8
P9
GNDP
P10
P11
PMRQL
PFXGNTL
PFXSTS
POE1L
PIMCKSTRDL
VMIDSL
VMIVS
VDDP
VMIHSEL0
VMIHSEL1
VMIHSEL2
VMIRWL
SDA
AGND
SR
SG
SB
157
158
159
160
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166
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105
VSYNCB
HSYNCL
BLANKL
TMCLK
TDCLK
PENFEATL
PCLK
GNDP
P7
P6
P5
P4
P3
P2
P1
P0
GNDP
MD63
MD62
MD61
MD60
MD59
MD58
MD57
GND
MD56
MD55
MD54
MD53
MD52
MD51
MD50
MD49
VDDP
MD48
MD47
MD46
MD45
MD44
MD43
MD42
MD41
MD40
GNDP
MD39
MD38
MD37
MD36
MD35
MD34
MD33
MD32
MX86251
104
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PCAS7L
PCAS6L
PCAS5L
PCAS4L
GNDP
POE0L
PRAS1L
PWE1L
GND
PRASB0
PWEB0
VDDP
PMA8
PMA7
PMA6
PMA5
PMA4
PMA3
GND
PMA2
PMA1
PMA0
PCAS0L
PCAS1L
PCAS2L
PCAS3L
MD0
MD1
MD2
MD3
MD4
GNDP
MD5
MD6
MD7
MD8
MD9
MD10
MD11
GNDP
MD12
MD13
MD14
MD15
MD16
MD17
MD18
VDDP
MD19
MD20
MD21
MD22
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AVDD
SIREF
AGND
SVREF
SCK
PAD31
PAD30
PAD29
PAD28
PAD27
VDD
PAD26
PAD25
PAD24
PAD23
PAD22
PAD21
PAD20
PAD19
PAD18
GNDP
PAD17
PAD16
PAD15
PAD14
PAD13
PAD12
PAD11
PAD10
VDDP
PAD9
PAD8
PAD7
PAD6
PAD5
PAD4
PAD3
PAD2
GND
PAD1
PAD0
ROMOEL
MD31
MD30
MD29
MD28
MD27
GNDP
MD26
MD25
MD24
MD23
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MX86251
2.Functional Description
The MX86251 is a new generation of fully integrated graphics and video accelerator with the high performance VR
interface to 3Dfx’s Voodoo Rush chip set to achieve the leading-edge 3D effect. On a single chip, it integrates a 64-
bit graphics CoProcessor, a true-color video processor, 160MHz RAMDAC and dual programmable clock synthe-
sizer. The MX86251 not only delivers extreme high performance in 3D/2D graphics acceleration, it also provides
very rich functionality for motion video applications. The MX86251 true color video processor allows full screen full
motion playback of AVI and MPEG video from software based Codec’s such as MPEG, Cinepak and Indeo. For
even higher quality MPEG video playback, the MX86251 Media port supports the VMI connector linking to an
external MPEG-1 decoder chip. The Media port also provides for playback and capture of live video input from TV
tuner or video camera.
2.1 MX86251 chip function block diagram
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MX86251
2.2 64-bit Graphics Co-processor
The MX86251 Graphics Co-processor accelerates com-
mon Graphics User Interface drawing functions , includ-
ing Bitblt, Rectangle Fill, Pattern Fill, Bresenham Line
Draw, and Text Transfer. Hardware clipping and hardware
cursor further reduce software driver overhead, includ-
ing Bitblt, Rectangle Fill, Pattern Fill, Bresenham Line
Draw, and Text Transfer. Hardware clipping and hardware
cursor further reduce software driver overhead to the
minimum.
The Graphics Co-processor supports scrardware cursor
further rr further reduce software driver overhead to the
minimum.
The Graphics Co-processor supports screen widths of
640, 800, 1024, 1152, 1280, 1600 and 2048. Pixel depth
can be 8, 16, and 32 bits. The display memory size can
be 1,2 or 4 megabytes. All Co-processor drawing opera-
tions are programmed with 32 bit registers in a linear
address aperture.
Pattern Map Buffer
The most common Bitblt operation in Windows is the
PatBlt which means painting a large window background
using a brush which is an 8 by 8 pattern bitmap. Many
GUI chips store the brush pattern bitmap in offscreen
memory. During Patblt, the pattern are fetched repeat-
edly.
To accelerate Patblt, the MX86251 has on-chip memory
to store a full 8 by 8 pattern bitmap. Unlike others which
can only store 8-bit pixels, The MX86251 can store pixel
maps of 8, 16, and 32 bit pixels. This complete imple-
mentation of Pattern Map, enables the MX86251 to ex-
ecute the Patblts at peak memory bandwidth using a long
burst of page mode writes and thus achieving the best
drawing performance.
Text / Font drawing acceleration
Drawing text characters or fonts are another very com-
mon Windows drawing operation. The fonts are mono-
chrome bitmaps that get expanded into color pixel maps
in the Graphics Co-processor. The MX86251 optimizes
this process in several ways.
Font bitmaps can be stored in system memory and trans-
ferred to the Co-processor for color expansion.The
MX86251 provides a screen port to facilitate this memory
to screen transfer. The screen port is mapped in a linear
address aperture of 64K bytes. The monochrome font
pixels are buffered in the Source FIFO so that concur-
rent operations are enabled for font transfer from system
memory and color expansion in the Co-processor. The
display driver can also cache font bitmaps in offscreen
memory using the so called font-cache scheme. The
MX86251 provides direct support of offscreen packed
monochrome bitmap to color map expansion. This op-
eration greatly accelerates the performance of font cache.
Three Operand Bitblt
The Graphics Co-processor executes Bitblt operations
between three operands: the Source bitmap, the Desti-
nation bitmap, and the Pattern bitmap. There are 256
operations on bitmaps, called Raster Operations (ROP).
An ALU with three operand inputs is implemented to ex-
ecute any of the 256 RO P ’s in a single cycle, unlike ear-
lier generation GUI chips which used only two operands
and implemented only 16 ROPs. This forced the soft-
ware driver to decompose those 3-operand bitblt into
two or three 2-operand BitBLTs significantly slowing down
the drawing process.
Source/Destination FIFOs
The three inputs to the Bitblt ALU are from the Source
FIFO, the Destination FIFO and the Pattern Map Buffer.
The Source and Destination FIFO are 64 bit wide and 8
levels deep. They allow the fetch cycles for Source and
Destination pixels to be run in page mode cycles. By hav-
ing Destination FIFO, the MX86251 can run Destination
read-modify-write operations in page mode reads followed
by page mode writes which is substantially faster than
the read-modify-write cycles in an EDO-DRAM based
system.
Windows 95 Direct Draw acceleration
Windows 95 Direct Draw is aimed to turn the Windows
GUI environment into a Game platform with high speed
sprite animation. The key to sprite animation is Transpar-
ent Blt. The MX86251 implements a flexible Color Key
mechanism to enable high speed Transparent Blt. A Trans-
parent Blt writes to screen a source bitmap, that is, a
sprite, which is in an irregular shape such as a cartoon
figure. The background pixels which should not be over-
written are coded in the special Key color. The Color Com-
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