HY29F800A
8 Megabit (1Mx8/512Kx16), 5 Volt-only, Flash Memory
KEY FEATURES
n
5 Volt Read, Program, and Erase
– Minimizes system-level power requirements
n
High Performance
– Access times as fast as 50 ns
n
Low Power Consumption
– 20 mA typical active read current in byte
mode, 28 mA typical in word mode
– 35 mA typical program/erase current
– 5 µA maximum CMOS standby current
n
Compatible with JEDEC Standards
– Package, pinout and command-set
compatible with the single-supply Flash
device standard
– Provides superior inadvertent write
protection
n
Sector Erase Architecture
– Boot sector architecture with top and
bottom boot block options available
– One 16 Kbyte, two 8 Kbyte, one 32 Kbyte
and fifteen 64 Kbyte sectors in byte mode
– One 8 Kword, two 4 Kword, one 16 Kword
and fifteen 32 Kword sectors in word mode
– A command can erase any combination of
sectors
– Supports full chip erase
n
Erase Suspend/Resume
– Temporarily suspends a sector erase
operation to allow data to be read from, or
programmed into, any sector not being
erased
GENERAL DESCRIPTION
The HY29F800A is an 8 Megabit, 5 volt only CMOS
Flash memory organized as 1,048,576 (1M) bytes
or 524,288 (512K) words. The device is offered in
industry-standard 44-pin PSOP and 48-pin TSOP
packages.
The HY29F800A can be programmed and erased
in-system with a single 5-volt V
CC
supply. Internally
generated and regulated voltages are provided for
program and erase operations, so that the device
does not require a high voltage power supply to
perform those functions. The device can also be
programmed in standard EPROM programmers.
Access times as fast as 55 ns over the full operat-
ing voltage range of 5.0 volts ± 10% are offered for
timing compatibility with the zero wait state require-
ments of high speed microprocessors. A 50 ns
Preliminary
Revision 1.1, February 2002
n
Sector Protection
– Any combination of sectors may be locked
to prevent program or erase operations
within those sectors
n
Temporary Sector Unprotect
– Allows changes in locked sectors
(requires high voltage on RESET# pin)
n
Internal Erase Algorithm
– Automatically erases a sector, any
combination of sectors, or the entire chip
n
Internal Programming Algorithm
– Automatically programs and verifies data
at a specified address
n
Fast Program and Erase Times
– Byte programming time: 7 µs typical
– Sector erase time: 1.0 sec typical
– Chip erase time: 19 sec typical
n
Data# Polling and Toggle Status Bits
– Provide software confirmation of
completion of program or erase
operations
n
Ready/Busy# Output (RY/BY#)
– Provides hardware confirmation of
completion of program and erase
operations
n
Minimum 100,000 Program/Erase Cycles
n
Space Efficient Packaging
– Available in industry-standard 44-pin
PSOP and 48-pin TSOP and reverse
TSOP packages
LOGIC DIAGRAM
19
A[18:0]
DQ[7:0]
7
CE#
OE#
WE#
RESET#
BYTE#
RY/BY#
DQ[14:8]
DQ[15]/A-1
8
HY29F800A
version operating over 5.0 volts ± 5% is also avail-
able. To eliminate bus contention, the HY29F800A
has separate chip enable (CE#), write enable
(WE#) and output enable (OE#) controls.
The device is compatible with the JEDEC single
power-supply Flash command set standard. Com-
mands are written to the command register using
standard microprocessor write timings, from where
they are routed to an internal state-machine that
controls the erase and programming circuits. De-
vice programming is performed a byte at a time
by executing the four-cycle Program Command.
This initiates an internal algorithm that automati-
cally times the program pulse widths and verifies
proper cell margin.
The HY29F800A’s sector erase architecture allows
any number of array sectors to be erased and re-
programmed without affecting the data contents
of other sectors. Device erasure is initiated by ex-
ecuting the Erase Command. This initiates an in-
ternal algorithm that automatically preprograms the
array (if it is not already programmed) before ex-
ecuting the erase operation. During erase cycles,
the device automatically times the erase pulse
widths and verifies proper cell margin.
To protect data in the device from accidental or
unauthorized attempts to program or erase the
device while it is in the system (e.g., by a virus),
BLOCK DIAGRAM
the device has a Sector Protect function which
hardware write protects selected sectors. The
sector protect and unprotect features can be en-
abled in a PROM programmer. Temporary Sector
Unprotect, which requires a high voltage, allows
in-system erasure and code changes in previously
protected sectors.
Erase Suspend enables the user to put erase on
hold for any period of time to read data from, or
program data to, any sector that is not selected
for erasure. True background erase can thus be
achieved. The device is fully erased when shipped
from the factory.
Addresses and data needed for the programming
and erase operations are internally latched during
write cycles, and the host system can detect
completion of a program or erase operation by
observing the RY/BY# pin, or by reading the DQ[7]
(Data# Polling) and DQ[6] (toggle) status bits.
Reading data from the device is similar to reading
from SRAM or EPROM devices. Hardware data
protection measures include a low V
CC
detector
that automatically inhibits write operations during
power transitions.
The host can place the device into the standby
mode. Power consumption is greatly reduced in
this mode.
DQ[15:0]
A[18:0], A-1
STATE
CONTROL
DQ[15:0]
WE#
CE#
OE#
BYTE#
RESET#
RY/BY#
PROGRAM
VOLTAGE
GENERATOR
COMMAND
REGISTER
ERASE VOLTAGE
GENERATOR AND
SECTOR SWITCHES
I/O CONTROL
I/O BUFFERS
DATA LATCH
V
C C
DETECTOR
TIMER
A[18:0], A-1
ADDRESS LATCH
Y-DECODER
Y-GATING
X-DECODER
8 Mb FLASH
MEMORY
ARRAY
2
Rev. 1.1/Feb 02
HY29F800A
PIN CONFIGURATIONS
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE#
V
SS
OE#
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RESET#
WE#
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
PSOP44
Standard
TSOP48
A16
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Reverse
TSOP48
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
CONVENTIONS
Unless otherwise noted, a positive logic (active
High) convention is assumed throughout this docu-
ment, whereby the presence at a pin of a higher,
more positive voltage (nominally 5VDC) causes
assertion of the signal. A ‘#’ symbol following the
signal name, e.g., RESET#, indicates that the sig-
nal is asserted in a Low state (nominally 0 volts).
Whenever a signal is separated into numbered bits,
e.g., DQ[7], DQ[6], ..., DQ[0], the family of bits may
also be shown collectively, e.g., as DQ[7:0].
The designation 0xNNNN (N = 0, 1, 2, . . . , 9, A, .
. . , E, F) indicates a number expressed in hexadeci-
mal notation. The designation 0bXXXX indicates a
number expressed in binary notation (X = 0, 1).
3
Rev. 1.1/Feb 02
HY29F800A
SIGNAL DESCRIPTIONS
Name
A[18:0]
Type
Description
Address, active High.
In word mode, these 19 inputs select one of 524,288
(512K) words within the array for read or write operations. In byte mode, these
Inputs
inputs are combined with the DQ[15]/A[-1] input (LSB) to select one of 1,048,576
(1M) bytes within the array for read or write operations.
Data Bus, active High
. In word mode, these pins provide a 16-bit data path
Inputs/Outputs for read and write operations. In byte mode, DQ[7:0] provide an 8-bit data path
Tri-state
and DQ[15]/A[-1] is used as the LSB of the 20-bit byte address input. DQ[14:8]
are unused and remain tri-stated in byte mode.
Byte Mode, active Low.
Controls the Byte/Word configuration of the device.
Input
Low selects byte mode, High selects word mode.
Chip Enable, active Low.
This input must be asserted to read data from or
Input
write data to the HY29F800A. When High, the data bus is tri-stated and the
device is placed in the Standby mode.
Output Enable, active Low
. This input must be asserted for read operations
and negated for write operations. BYTE# determines whether a byte or a word
Input
is read during the read operation. When High, data outputs from the device are
disabled and the data bus pins are placed in the high impedance state.
W r ite E n a b le , a c tiv e L o w.
C o ntro ls wri ti ng o f c o mma nd s o r c o mma nd
sequences in order to program data or erase sectors of the memory array. A
Input
write operation takes place when WE# is asserted while CE# is Low and OE#
is High. BYTE# determines whether a byte or a word is written during the write
operation.
Hardw are Reset, active Low.
Provides a hardware method of resetting the
HY29F800A to the read array state. When the device is reset, it immediately
Input
terminates any operation in progress. The data bus is tri-stated and all read/write
commands are ignored while the input is asserted. While RESET# is asserted,
the device will be in the Standby mode.
R e a d y /B u s y S ta tu s .
Ind i c a te s whe the r a wri te o r e ra s e c o mma nd i s i n
progress or has been completed. RY/BY# is valid after the rising edge of the
Output
final WE# pulse of a command sequence. It remains Low while the device is
Open Drain
actively programming data or erasing, and goes High when it is ready to read
array data.
5-volt (nominal) pow er supply.
--
--
Pow er and signal ground.
DQ[15]/A[-1],
DQ[14:0]
BYTE#
C E#
OE#
WE#
RESET#
RY/BY#
V
CC
V
SS
MEMORY ARRAY ORGANIZATION
The 1 Mbyte Flash memory array is organized into
nineteen blocks called
sectors
(S0, S1, . . . , S18).
A sector is the smallest unit that can be erased
and which can be protected to prevent accidental
or unauthorized erasure. See the ‘Bus Operations’
and ‘Command Definitions’ sections of this docu-
ment for additional information on these functions.
In the HY29F800A, four of the sectors, which com-
prise the
boot block,
vary in size from 8 to 32
Kbytes (4 to 16 Kwords), while the remaining fif-
teen sectors are uniformly sized at 64 Kbytes (32
Kwords). The boot block can be located at the
bottom of the address range (HY29F800AB) or at
the top of the address range (HY29F800AT).
Table 1 defines the sector addresses and corre-
sponding address ranges for the top and bottom
boot block versions of the HY29F800A.
4
Rev. 1.1/Feb 02
HY29F800A
Table 1. HY29F800A Memory Array Organization
Sector Address
1
Size
Byte Mode
Device Sector
(KB/KW) A[18] A[17] A[16] A[15] A[14] A[13] A[12] Address Range
2
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
32/16
8/4
8/4
16/8
16/8
8/4
8/4
32/16
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
1
1
0
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
X
X
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0x00000 - 0x0FFFF
0x10000 - 0x1FFFF
0x20000 - 0x2FFFF
0x30000 - 0x3FFFF
0x40000 - 0x4FFFF
0x50000 - 0x5FFFF
0x60000 - 0x6FFFF
0x70000 - 0x7FFFF
0x80000 - 0x8FFFF
0x90000 - 0x9FFFF
0xA0000 - 0xAFFFF
0xB0000 - 0xBFFFF
0xC0000 - 0xCFFFF
0xD0000 - 0xDFFFF
0xE0000 - 0xEFFFF
0xF0000 - 0xF7FFF
0xF8000 - 0xF9FFF
0xFA000 - 0xFBFFF
0xFC000 - 0xFFFFF
0x00000 - 0x03FFF
0x04000 - 0x05FFF
0x06000 - 0x07FFF
0x08000 - 0x0FFFF
0x10000 - 0x1FFFF
0x20000 - 0x2FFFF
0x30000 - 0x3FFFF
0x40000 - 0x4FFFF
0x50000 - 0x5FFFF
0x60000 - 0x6FFFF
0x70000 - 0x7FFFF
0x80000 - 0x8FFFF
0x90000 - 0x9FFFF
0xA0000 - 0xAFFFF
0xB0000 - 0xBFFFF
0xC0000 - 0xCFFFF
0xD0000 - 0xDFFFF
0xE0000 - 0xEFFFF
0xF0000 - 0xFFFFF
Word Mode
Address Range
3
0x00000 - 0x07FFF
0x08000 - 0x0FFFF
0x10000 - 0x17FFF
0x18000 - 0x1FFFF
0x20000 - 0x27FFF
0x28000 - 0x2FFFF
0x30000 - 0x37FFF
0x38000 - 0x3FFFF
0x40000 - 0x47FFF
0x48000 - 0x4FFFF
0x50000 - 0x57FFF
0x58000 - 0x5FFFF
0x60000 - 0x67FFF
0x68000 - 0x6FFFF
0x70000 - 0x77FFF
0x78000 - 0x7BFFF
0x7C000 - 0x7CFFF
0x7D000 - 0x7DFFF
0x7E000 - 0x7FFFF
0x00000 - 0x01FFF
0x02000 - 0x02FFF
0x03000 - 0x03FFF
0x04000 - 0x07FFF
0x08000 - 0x0FFFF
0x10000 - 0x17FFF
0x18000 - 0x1FFFF
0x20000 - 0x27FFF
0x28000 - 0x2FFFF
0x30000 - 0x37FFF
0x38000 - 0x3FFFF
0x40000 - 0x47FFF
0x48000 - 0x4FFFF
0x50000 - 0x57FFF
0x58000 - 0x5FFFF
0x60000 - 0x67FFF
0x68000 - 0x6FFFF
0x70000 - 0x77FFF
0x78000 - 0x7FFFF
Notes:
1. X indicates Don’t Care.
2. Address in Byte Mode is A[18:-1].
3. Address in Word Mode is A[18:0].
Rev. 1.1/Feb 02
HY29F800AB - Bottom Boot Block
HY29F800AT - Top Boot Block
5
TI技术论坛
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
