HY57V643220D(L/S)T(P) Series
4Banks x 512K x 32bits Synchronous DRAM
Document Title
4Bank x 512K x 32bits Synchronous DRAM
Revision History
Revision
No.
0.1
0.2
0.3
Initial Draft
Removed Preliminary
1. Updated Output Load Capacitance for Access Time Measurement CL = 30pF
in AC OPERATING TEST CONDITION
2. Updated the tolerance zone of the leads and the description of the package
type in PACKAGE DIMENSION
History
Draft Date
May. 2004
July 2004
Sep. 2004
Remark
Preliminary
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 0.3 / Sep. 2004
1
HY57V643220D(L/S)T(P) Series
4Banks x 512K x 32bits Synchronous DRAM
DESCRIPTION
The Hynix HY57V643220D(L/S)T(P) series is a 67,108,864bit CMOS Synchronous DRAM, ideally suited for the memory
applications which require wide data I/O and high bandwidth. HY57V643220D(L/S)T(P) is organized as 4banks of
524,228x32.
HY57V643220D(L/S)T(P) is offering fully synchronous operation referenced to a positive edge of the clock. All inputs
and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve
very high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(se-
quential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or
can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not re-
stricted by a '2N' rule)
FEATURES
•
•
•
•
•
•
Voltage : VDD, VDDQ 3.3V supply voltage
All device pins are compatible with LVTTL interface
JEDEC standard 400mil 86pin TSOP-II with 0.5mm of
pin pitch
All inputs and outputs referenced to positive edge of
system clock
Data mask function by DQM 0, 1, 2 and DQM 3
Internal four banks operation
•
•
•
•
•
Auto refresh and self refresh
4096 Refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
Programmable CAS Latency ; 2, 3 Clocks
Burst Read Single Write operation
ORDERING INFORMATION
Part No.
HY57V643220D(L/S)T(P)-45
HY57V643220D(L/S)T(P)-5
HY57V643220D(L/S)T(P)-55
HY57V643220D(L/S)T(P)-6
HY57V643220D(L/S)T(P)-7
Note
1. HY57V643220DT(P)
2. HY57V643220DLT(P)
3. HY57V643220DST(P)
4. HY57V643220D(L/S)T
5. HY57V643220D(L/S)TP
Clock
Frequency
222MHz
200MHz
183MHz
166MHz
143MHz
Organization
Interface
Package
4Banks x 512Kbits
x32
LVTTL
86pin TSOP-II
(Lead Free)
Series : Normal Power
Series : Low Power
Series : Super Low Power
Series : Leaded
Series : Lead Free
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 0.3 / Sep. 2004
2
HY57V643220D(L/S)T(P) Series
4Banks x 512K x 32bits Synchronous DRAM
86PIN TSOP II CONFIGURATION
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDD
DQM0
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
DQM2
VDD
NC
DQ16
VSSQ
DQ17
DQ18
VDDQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VDDQ
DQ23
VDD
1
2
3
86
85
84
20
21
22
86Pin TSOP II
400Mil x 875mil
0.5mm Pin Pitch
67
66
65
41
42
43
46
45
44
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
VSS
NC
DQ31
VDDQ
DQ30
DQ29
VSSQ
DQ28
DQ27
VDDQ
DQ26
DQ25
VSSQ
DQ24
VSS
Rev. 0.3 / Sep. 2004
3
HY57V643220D(L/S)T(P) Series
4Banks x 512K x 32bits Synchronous DRAM
Pin FUNCTION DESCRIPTIONS
Pin
CLK
CKE
CS
BA0, BA1
A0 ~ A10
Clock
Clock Enable
Chip Select
Bank Address
Address
Row Address Strobe,
Column Address Strobe,
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/
Ground
No Connection
Pin Name
DESCRIPTION
The system clock input. All other inputs are registered to the
SDRAM on the rising edge of CLK.
Controls internal clock signal and when deactivated, the SDRAM will
be one of the states among power down, suspend or self refresh
Enables or disables all inputs except CLK, CKE and DQM
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address : RA0 ~ RA10, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
RAS, CAS and WE define the operation
Refer function truth table for details
Controls output buffers in read mode and masks input data in write
mode
Multiplexed data input / output pin
Power supply for internal circuits and input buffers
Power supply for output buffers
No connection
RAS, CAS, WE
DQM0~3
DQ0 ~ DQ31
VDD/VSS
VDDQ/VSSQ
NC
Rev. 0.3 / Sep. 2004
4
HY57V643220D(L/S)T(P) Series
4Banks x 512K x 32bits Synchronous DRAM
FUNCTIONAL BLOCK DIAGRAM
512Kbit x 4banks x 32 I/O Low Power Synchronous DRAM
Self refresh
logic & timer
Internal Row
Counter
CLK
CKE
State Machine
Row Active
512Kx32 BANK 3
Row
Pre
Decoder
512Kx32 BANK 2
512Kx32 BANK 1
512Kx32 BANK 0
DQ0
I/O Buffer & Logic
Sense AMP & I/O Gate
X-Decoder
X-Decoder
X-Decoder
X-Decoder
CS
RAS
CAS
Refresh
Memory
Cell
Array
Column Active
WE
DQM0~3
Column
Pre
Decoder
DQ31
Y-Decoder
Bank Select
Column Add
Counter
A0
A1
Address Buffers
Address
Register
Burst
Counter
A10
BA1
BA0
Mode Register
CAS Latency
Data Out Control
Pipe Line
Control
Rev. 0.3 / Sep. 2004
5
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