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HY57V64420HGLT-H: 产品描述4 Banks x 4M x 4Bit Synchronous DRAM; 产品类别存储存储; 文件大小139KB，共11页; 制造商SK Hynix(海力士); 官网地址http://www.hynix.com/eng/

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HY57V64420HGLT-H概述

4 Banks x 4M x 4Bit Synchronous DRAM

HY57V64420HGLT-H规格参数

参数名称	属性值
厂商名称	SK Hynix(海力士)
零件包装代码	TSOP2
包装说明	TSOP2, TSOP54,.46,32
针数	54
Reach Compliance Code	unknow
ECCN代码	EAR99
访问模式	FOUR BANK PAGE BURST
最长访问时间	5.4 ns
其他特性	AUTO/SELF REFRESH
最大时钟频率 (fCLK)	133 MHz
I/O 类型	COMMON
交错的突发长度	1,2,4,8
JESD-30 代码	R-PDSO-G54
JESD-609代码	e6
长度	22.238 mm
内存密度	67108864 bi
内存集成电路类型	SYNCHRONOUS DRAM
内存宽度	4
功能数量	1
端口数量	1
端子数量	54
字数	16777216 words
字数代码	16000000
工作模式	SYNCHRONOUS
最高工作温度	70 °C
最低工作温度
组织	16MX4
输出特性	3-STATE
封装主体材料	PLASTIC/EPOXY
封装代码	TSOP2
封装等效代码	TSOP54,.46,32
封装形状	RECTANGULAR
封装形式	SMALL OUTLINE, THIN PROFILE
电源	3.3 V
认证状态	Not Qualified
刷新周期	4096
座面最大高度	1.194 mm
自我刷新	YES
连续突发长度	1,2,4,8,FP
最大待机电流	0.002 A
最大压摆率	0.16 mA
最大供电电压 (Vsup)	3.6 V
最小供电电压 (Vsup)	3 V
标称供电电压 (Vsup)	3.3 V
表面贴装	YES
技术	CMOS
温度等级	COMMERCIAL
端子面层	TIN BISMUTH
端子形式	GULL WING
端子节距	0.8 mm
端子位置	DUAL
宽度	10.16 mm

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HY57V64420HG

4 Banks x 4M x 4Bit Synchronous DRAM

DESCRIPTION

The Hynix HY57V64420HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which

require large memory density and high bandwidth. HY57V64420HG is organized as 4banks of 4,194,304x4.

HY57V644020HG is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-

nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output

voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by

a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of read

or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or

write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)

FEATURES

•

Single 3.3±0.3V power supply

All device pins are compatible with LVTTL interface

JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin

pitch

All inputs and outputs referenced to positive edge of system

clock

Data mask function by DQM

Internal four banks operation

•

Auto refresh and self refresh

4096 refresh cycles / 64ms

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or Full page for Sequential Burst

•

- 1, 2, 4 or 8 for Interleave Burst

Programmable CAS Latency ; 2, 3 Clocks

•

ORDERING INFORMATION

Part No.

HY57V64420HGT-5/55/6/7

HY57V64420HGT-K

HY57V64420HGT-H

HY57V64420HGT-P

HY57V64420HGT-S

HY57V64420HGLT-5/55/6/7

HY57V64420HGLT-K

HY57V64420HGLT-H

HY57V64420HGLT-P

HY57V64420HGLT-S

Clock Frequency

200/183/166/143MHz

133MHz

100MHz

200/183/166/143MHz

133MHz

100MHz

Power

Organization

Interface

Package

Normal

4Banks x 4Mbits x4

LVTTL

400mil 54pin TSOP II

Low power

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of

circuits described. No patent licenses are implied.

Rev. 0.4/Nov. 01

HY57V64420HGLT-H相似产品对比

	HY57V64420HGLT-H	HY57V64420HG	HY57V64420HGT-H	HY57V64420HGT-P	HY57V64420HGT-S	HY57V64420HGLT-K
描述	4 Banks x 4M x 4Bit Synchronous DRAM	4 Banks x 4M x 4Bit Synchronous DRAM	4 Banks x 4M x 4Bit Synchronous DRAM	4 Banks x 4M x 4Bit Synchronous DRAM	4 Banks x 4M x 4Bit Synchronous DRAM	4 Banks x 4M x 4Bit Synchronous DRAM
厂商名称	SK Hynix(海力士)	-	SK Hynix(海力士)	SK Hynix(海力士)	SK Hynix(海力士)	SK Hynix(海力士)
零件包装代码	TSOP2	-	TSOP2	TSOP2	TSOP2	TSOP2
包装说明	TSOP2, TSOP54,.46,32	-	TSOP2, TSOP54,.46,32	TSOP2, TSOP54,.46,32	TSOP2, TSOP54,.46,32	TSOP2, TSOP54,.46,32
针数	54	-	54	54	54	54
Reach Compliance Code	unknow	-	unknow	unknow	unknow	unknow
ECCN代码	EAR99	-	EAR99	EAR99	EAR99	EAR99
访问模式	FOUR BANK PAGE BURST	-	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
最长访问时间	5.4 ns	-	5.4 ns	6 ns	6 ns	5.4 ns
其他特性	AUTO/SELF REFRESH	-	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
最大时钟频率 (fCLK)	133 MHz	-	133 MHz	100 MHz	100 MHz	133 MHz
I/O 类型	COMMON	-	COMMON	COMMON	COMMON	COMMON
交错的突发长度	1,2,4,8	-	1,2,4,8	1,2,4,8	1,2,4,8	1,2,4,8
JESD-30 代码	R-PDSO-G54	-	R-PDSO-G54	R-PDSO-G54	R-PDSO-G54	R-PDSO-G54
JESD-609代码	e6	-	e6	e6	e6	e6
长度	22.238 mm	-	22.238 mm	22.238 mm	22.238 mm	22.238 mm
内存密度	67108864 bi	-	67108864 bi	67108864 bi	67108864 bi	67108864 bi
内存集成电路类型	SYNCHRONOUS DRAM	-	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM
内存宽度	4	-	4	4	4	4
功能数量	1	-	1	1	1	1
端口数量	1	-	1	1	1	1
端子数量	54	-	54	54	54	54
字数	16777216 words	-	16777216 words	16777216 words	16777216 words	16777216 words
字数代码	16000000	-	16000000	16000000	16000000	16000000
工作模式	SYNCHRONOUS	-	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	70 °C	-	70 °C	70 °C	70 °C	70 °C
组织	16MX4	-	16MX4	16MX4	16MX4	16MX4
输出特性	3-STATE	-	3-STATE	3-STATE	3-STATE	3-STATE
封装主体材料	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	TSOP2	-	TSOP2	TSOP2	TSOP2	TSOP2
封装等效代码	TSOP54,.46,32	-	TSOP54,.46,32	TSOP54,.46,32	TSOP54,.46,32	TSOP54,.46,32
封装形状	RECTANGULAR	-	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	SMALL OUTLINE, THIN PROFILE	-	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE
电源	3.3 V	-	3.3 V	3.3 V	3.3 V	3.3 V
认证状态	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified
刷新周期	4096	-	4096	4096	4096	4096
座面最大高度	1.194 mm	-	1.194 mm	1.194 mm	1.194 mm	1.194 mm
自我刷新	YES	-	YES	YES	YES	YES
连续突发长度	1,2,4,8,FP	-	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP
最大待机电流	0.002 A	-	0.002 A	0.002 A	0.002 A	0.002 A
最大压摆率	0.16 mA	-	0.16 mA	0.16 mA	0.16 mA	0.16 mA
最大供电电压 (Vsup)	3.6 V	-	3.6 V	3.6 V	3.6 V	3.6 V
最小供电电压 (Vsup)	3 V	-	3 V	3 V	3 V	3 V
标称供电电压 (Vsup)	3.3 V	-	3.3 V	3.3 V	3.3 V	3.3 V
表面贴装	YES	-	YES	YES	YES	YES
技术	CMOS	-	CMOS	CMOS	CMOS	CMOS
温度等级	COMMERCIAL	-	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
端子面层	TIN BISMUTH	-	TIN BISMUTH	TIN BISMUTH	TIN BISMUTH	TIN BISMUTH
端子形式	GULL WING	-	GULL WING	GULL WING	GULL WING	GULL WING
端子节距	0.8 mm	-	0.8 mm	0.8 mm	0.8 mm	0.8 mm
端子位置	DUAL	-	DUAL	DUAL	DUAL	DUAL
宽度	10.16 mm	-	10.16 mm	10.16 mm	10.16 mm	10.16 mm

HY57V64420HGLT-H

HY57V64420HGLT-H概述

HY57V64420HGLT-H规格参数

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