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Datasheet> 器件分类 > 存储> 存储> HY5DS573222FP-4
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HY5DS573222FP-4

产品描述256M(8Mx32) GDDR SDRAM
产品类别存储    存储   
文件大小316KB，共28页
制造商SK Hynix(海力士)
官网地址http://www.hynix.com/eng/
标准
下载文档 详细参数 选型对比 全文预览

HY5DS573222FP-4概述

256M(8Mx32) GDDR SDRAM

HY5DS573222FP-4规格参数

参数名称属性值
是否Rohs认证符合
厂商名称SK Hynix(海力士)
零件包装代码BGA
包装说明LFBGA, BGA144,12X12,32
针数144
Reach Compliance Codeunknow
ECCN代码EAR99
访问模式FOUR BANK PAGE BURST
最长访问时间0.6 ns
其他特性AUTO/SELF REFRESH
最大时钟频率 (fCLK)250 MHz
I/O 类型COMMON
交错的突发长度2,4,8
JESD-30 代码S-PBGA-B144
JESD-609代码e1
长度12 mm
内存密度268435456 bi
内存集成电路类型DDR DRAM
内存宽度32
功能数量1
端口数量1
端子数量144
字数8388608 words
字数代码8000000
工作模式SYNCHRONOUS
最高工作温度70 °C
最低工作温度
组织8MX32
输出特性3-STATE
封装主体材料PLASTIC/EPOXY
封装代码LFBGA
封装等效代码BGA144,12X12,32
封装形状SQUARE
封装形式GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）260
电源1.8 V
认证状态Not Qualified
刷新周期4096
座面最大高度1.3 mm
自我刷新YES
连续突发长度2,4,8
最大供电电压 (Vsup)2.1 V
最小供电电压 (Vsup)1.75 V
标称供电电压 (Vsup)1.8 V
表面贴装YES
技术CMOS
温度等级COMMERCIAL
端子面层Tin/Silver/Copper (Sn/Ag/Cu)
端子形式BALL
端子节距0.8 mm
端子位置BOTTOM
处于峰值回流温度下的最长时间20
宽度12 mm
Base Number Matches1

HY5DS573222FP-4文档预览

HY5DS573222F(P)
256M(8Mx32) GDDR SDRAM
HY5DS573222F(P)
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.0 / Feb. 2005
1
1HY5DS573222F(P)
Revision History
No.
0.1
0.2
0.3
0.4
0.5
1.0
Defined Target Spec.
Supports Lead free parts for each speed grade
CL, AC parameter, IDD5 change
CL, tCK_max, tRAS, tDAL change & Comment of DLL_off condition
1) Changed IDD & VDD_max
2) Changed tRCDWR, tWR, CL, tCK_max at 350Mhz speed bin
Version 1.0 Release
History
Draft Date
Mar. 2004
Apr. 2004
Apr. 2004
Jun. 2004
Oct. 2004
Feb. 2005
Remark
Rev. 1.0 / Feb. 2005
2
1HY5DS573222F(P)
DESCRIPTION
The Hynix HY5DS573222 is a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the
point-to-point applications which requires high bandwidth.
The Hynix 8Mx32 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
FEATURES
•
•
•
•
•
•
•
•
The Hynix HY5DS573222F(P) guarantee until
166MHz speed at DLL_off condition
1.8V V
DD
and V
DDQ
wide range max
power supply
supports
All inputs and outputs are compatible with SSTL_2
interface
12mm x 12mm, 144ball FBGA with 0.8mm pin pitch
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous - data transaction aligned to
bidirectional data strobe (DQS0 ~ DQS3)
Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
•
•
Data(DQ) and Write masks(DM) latched on the both
rising and falling edges of the data strobe
All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock
Write mask byte controls by DM (DM0 ~ DM3)
Programmable /CAS Latency 5 / 4 supported
Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
Internal 4 bank operations with single pulsed /RAS
tRAS Lock-Out function supported
Auto refresh and self refresh supported
4096 refresh cycles / 32ms
Half strength and Matched Impedance driver option
•
•
•
•
•
•
•
•
ORDERING INFORMATION
Part No.
HY5DS573222F(P)-28
HY5DS573222F(P)-33
HY5DS573222F(P)-36
HY5DS573222F(P)-4
V
DD
/V
DDQ
1.8V
Power Supply
Clock
Frequency
350MHz
300MHz
275MHz
250MHz
Max Data Rate
700Mbps/pin
600Mbps/pin
550Mbps/pin
500Mbps/pin
SSTL_2
12mm x 12mm
144Ball FBGA
interface
Package
Note) Hynix supports Lead free parts for each speed grade with same specification, except Lead free materials.
We'll add "P" character after "F" for lead free product.
For example, the part number of 300Mhz Lead free product is HY5DS573222FP-33.
Rev. 1.0 / Feb. 2005
3
1HY5DS573222F(P)
PIN CONFIGURATION
(Top View)
ROW and COLUMN ADDRESS TABLE
Items
Organization
Row Address
Column Address
Bank Address
Auto Precharge Flag
Refresh
8Mx32
2M x 32 x 4banks
A0 ~ A11
A0 ~ A7, A9
BA0, BA1
A8
4K
Rev. 1.0 / Feb. 2005
4
1HY5DS573222F(P)
PIN DESCRIPTION
PIN
CK, /CK
TYPE
Input
DESCRIPTION
Clock: CK and /CK are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of /CK. Output
(read) data is referenced to the crossings of CK and /CK (both directions of crossing).
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER
DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row
ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF
REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE
must be maintained high throughout READ and WRITE accesses. Input buffers, excluding
CK, /CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are
disabled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW
level after Vdd is applied.
Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All com-
mands are masked when CS is registered high. CS provides for external bank selection on
systems with multiple banks. CS is considered part of the command code.
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRE-
CHARGE command is being applied.
Address Inputs: Provide the row address for ACTIVE commands, and the column address
and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the
memory array in the respective bank. A8 is sampled during a precharge command to
determine whether the PRECHARGE applies to one bank (A8 LOW) or all banks (A8
HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The
address inputs also provide the op code during a MODE REGISTER SET command. BA0
and BA1 define which mode register is loaded during the MODE REGISTER SET command
(MRS or EMRS).
Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being
entered.
Input Data Mask: DM(0~3) is an input mask signal for write data. Input data is masked
when DM is sampled HIGH along with that input data during a WRITE access. DM is sam-
pled on both edges of DQS. Although DM pins are input only, the DM loading matches the
DQ and DQS loading. DM0 corresponds to the data on DQ0-Q7; DM1 corresponds to the
data on DQ8-Q15; DM2 corresponds to the data on DQ16-Q23; DM3 corresponds to the
data on DQ24-Q31.
Data Strobe: Output with read data, input with write data. Edge aligned with read data,
centered in write data. Used to capture write data. DQS0 corresponds to the data on
DQ0-Q7; DQS1 corresponds to the data on DQ8-Q15; DQS2 corresponds to the data on
DQ16-Q23; DQS3 corresponds to the data on DQ24-Q31
Data input / output pin : Data Bus
Power supply for internal circuits and input buffers.
Power supply for output buffers for noise immunity.
Reference voltage for inputs for SSTL interface.
No connection.
CKE
Input
/CS
Input
BA0, BA1
Input
A0 ~ A11
Input
/RAS, /CAS, /WE
Input
DM0 ~ DM3
Input
DQS0 ~ DQS3
I/O
DQ0 ~ DQ31
V
DD
/V
SS
V
DDQ
/V
SSQ
V
REF
NC
I/O
Supply
Supply
Supply
NC
Rev. 1.0 / Feb. 2005
5
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HY5DS573222FP-4相似产品对比

HY5DS573222FP-4 HY5DS573222F HY5DS573222F-28 HY5DS573222F-33 HY5DS573222FP HY5DS573222FP-36 HY5DS573222F-4 HY5DS573222FP-33 HY5DS573222FP-28 HY5DS573222F-36
描述 256M(8Mx32) GDDR SDRAM 256M(8Mx32) GDDR SDRAM 256M(8Mx32) GDDR SDRAM 256M(8Mx32) GDDR SDRAM 256M(8Mx32) GDDR SDRAM 256M(8Mx32) GDDR SDRAM 256M(8Mx32) GDDR SDRAM 256M(8Mx32) GDDR SDRAM 256M(8Mx32) GDDR SDRAM 256M(8Mx32) GDDR SDRAM
是否Rohs认证 符合 - 不符合 不符合 - 符合 不符合 符合 符合 不符合
厂商名称 SK Hynix(海力士) - SK Hynix(海力士) SK Hynix(海力士) - SK Hynix(海力士) SK Hynix(海力士) SK Hynix(海力士) SK Hynix(海力士) SK Hynix(海力士)
零件包装代码 BGA - BGA BGA - BGA BGA BGA BGA BGA
包装说明 LFBGA, BGA144,12X12,32 - LFBGA, BGA144,12X12,32 LFBGA, BGA144,12X12,32 - LFBGA, BGA144,12X12,32 LFBGA, BGA144,12X12,32 LFBGA, BGA144,12X12,32 LFBGA, BGA144,12X12,32 LFBGA, BGA144,12X12,32
针数 144 - 144 144 - 144 144 144 144 144
Reach Compliance Code unknow - unknow unknow - unknow unknow unknow unknow unknow
ECCN代码 EAR99 - EAR99 EAR99 - EAR99 EAR99 EAR99 EAR99 EAR99
访问模式 FOUR BANK PAGE BURST - FOUR BANK PAGE BURST FOUR BANK PAGE BURST - FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST
最长访问时间 0.6 ns - 0.6 ns 0.6 ns - 0.6 ns 0.6 ns 0.6 ns 0.6 ns 0.6 ns
其他特性 AUTO/SELF REFRESH - AUTO/SELF REFRESH AUTO/SELF REFRESH - AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH
最大时钟频率 (fCLK) 250 MHz - 350 MHz 300 MHz - 275 MHz 250 MHz 300 MHz 350 MHz 275 MHz
I/O 类型 COMMON - COMMON COMMON - COMMON COMMON COMMON COMMON COMMON
交错的突发长度 2,4,8 - 2,4,8 2,4,8 - 2,4,8 2,4,8 2,4,8 2,4,8 2,4,8
JESD-30 代码 S-PBGA-B144 - S-PBGA-B144 S-PBGA-B144 - S-PBGA-B144 S-PBGA-B144 S-PBGA-B144 S-PBGA-B144 S-PBGA-B144
JESD-609代码 e1 - e0 e0 - e1 e0 e1 e1 e0
长度 12 mm - 12 mm 12 mm - 12 mm 12 mm 12 mm 12 mm 12 mm
内存密度 268435456 bi - 268435456 bi 268435456 bi - 268435456 bi 268435456 bi 268435456 bi 268435456 bi 268435456 bi
内存集成电路类型 DDR DRAM - DDR DRAM DDR DRAM - DDR DRAM DDR DRAM DDR DRAM DDR DRAM DDR DRAM
内存宽度 32 - 32 32 - 32 32 32 32 32
功能数量 1 - 1 1 - 1 1 1 1 1
端口数量 1 - 1 1 - 1 1 1 1 1
端子数量 144 - 144 144 - 144 144 144 144 144
字数 8388608 words - 8388608 words 8388608 words - 8388608 words 8388608 words 8388608 words 8388608 words 8388608 words
字数代码 8000000 - 8000000 8000000 - 8000000 8000000 8000000 8000000 8000000
工作模式 SYNCHRONOUS - SYNCHRONOUS SYNCHRONOUS - SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
最高工作温度 70 °C - 70 °C 70 °C - 70 °C 70 °C 70 °C 70 °C 70 °C
组织 8MX32 - 8MX32 8MX32 - 8MX32 8MX32 8MX32 8MX32 8MX32
输出特性 3-STATE - 3-STATE 3-STATE - 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE
封装主体材料 PLASTIC/EPOXY - PLASTIC/EPOXY PLASTIC/EPOXY - PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 LFBGA - LFBGA LFBGA - LFBGA LFBGA LFBGA LFBGA LFBGA
封装等效代码 BGA144,12X12,32 - BGA144,12X12,32 BGA144,12X12,32 - BGA144,12X12,32 BGA144,12X12,32 BGA144,12X12,32 BGA144,12X12,32 BGA144,12X12,32
封装形状 SQUARE - SQUARE SQUARE - SQUARE SQUARE SQUARE SQUARE SQUARE
封装形式 GRID ARRAY, LOW PROFILE, FINE PITCH - GRID ARRAY, LOW PROFILE, FINE PITCH GRID ARRAY, LOW PROFILE, FINE PITCH - GRID ARRAY, LOW PROFILE, FINE PITCH GRID ARRAY, LOW PROFILE, FINE PITCH GRID ARRAY, LOW PROFILE, FINE PITCH GRID ARRAY, LOW PROFILE, FINE PITCH GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度） 260 - NOT SPECIFIED NOT SPECIFIED - 260 NOT SPECIFIED 260 260 NOT SPECIFIED
电源 1.8 V - 1.8 V 1.8 V - 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V
认证状态 Not Qualified - Not Qualified Not Qualified - Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
刷新周期 4096 - 4096 4096 - 4096 4096 4096 4096 4096
座面最大高度 1.3 mm - 1.3 mm 1.3 mm - 1.3 mm 1.3 mm 1.3 mm 1.3 mm 1.3 mm
自我刷新 YES - YES YES - YES YES YES YES YES
连续突发长度 2,4,8 - 2,4,8 2,4,8 - 2,4,8 2,4,8 2,4,8 2,4,8 2,4,8
最大供电电压 (Vsup) 2.1 V - 2.1 V 2.1 V - 2.1 V 2.1 V 2.1 V 2.1 V 2.1 V
最小供电电压 (Vsup) 1.75 V - 1.75 V 1.75 V - 1.75 V 1.75 V 1.75 V 1.75 V 1.75 V
标称供电电压 (Vsup) 1.8 V - 1.8 V 1.8 V - 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V
表面贴装 YES - YES YES - YES YES YES YES YES
技术 CMOS - CMOS CMOS - CMOS CMOS CMOS CMOS CMOS
温度等级 COMMERCIAL - COMMERCIAL COMMERCIAL - COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
端子面层 Tin/Silver/Copper (Sn/Ag/Cu) - Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) - Tin/Silver/Copper (Sn/Ag/Cu) Tin/Lead (Sn/Pb) Tin/Silver/Copper (Sn/Ag/Cu) Tin/Silver/Copper (Sn/Ag/Cu) Tin/Lead (Sn/Pb)
端子形式 BALL - BALL BALL - BALL BALL BALL BALL BALL
端子节距 0.8 mm - 0.8 mm 0.8 mm - 0.8 mm 0.8 mm 0.8 mm 0.8 mm 0.8 mm
端子位置 BOTTOM - BOTTOM BOTTOM - BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM
处于峰值回流温度下的最长时间 20 - NOT SPECIFIED NOT SPECIFIED - 20 NOT SPECIFIED 20 20 NOT SPECIFIED
宽度 12 mm - 12 mm 12 mm - 12 mm 12 mm 12 mm 12 mm 12 mm

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