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HY5DU561622CT-D: 产品描述256M-P DDR SDRAM; 文件大小238KB，共34页; 制造商SK Hynix(海力士); 官网地址http://www.hynix.com/eng/

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HY5DU561622CT-D概述

256M-P DDR SDRAM

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HY5DU56422CT-D4/D43

HY5DU56822CT-D4/D43

HY5DU561622CT-D4/D43

256M-P DDR SDRAM

HY5DU56422CT-D4/D43

HY5DU56822CT-D4/D43

HY5DU561622CT-D4/D43

This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume

any responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.3 / Oct. 2003

HY5DU56422CT-D4/D43

HY5DU56822CT-D4/D43

HY5DU561622CT-D4/D43

PIN DESCRIPTION

CK, /CK

TYPE

Input

DESCRIPTION

Clock: CK and /CK are differential clock inputs. All address and control input signals are

sampled on the crossing of the positive edge of CK and negative edge of /CK. Output

(read) data is referenced to the crossings of CK and /CK (both directions of crossing).

Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and

device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER

DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row

ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF

REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE

must be maintained high throughout READ and WRITE accesses. Input buffers, excluding

CK, /CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are

disabled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW

level after Vdd is applied.

Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All com-

mands are masked when CS is registered high. CS provides for external bank selection on

systems with multiple banks. CS is considered part of the command code.

Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRE-

CHARGE command is being applied.

Address Inputs: Provide the row address for ACTIVE commands, and the column address

and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the

memory array in the respective bank. A10 is sampled during a precharge command to

determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10

HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The

address inputs also provide the op code during a MODE REGISTER SET command. BA0

and BA1 define which mode register is loaded during the MODE REGISTER SET command

(MRS or EMRS).

Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being

entered.

Input Data Mask: DM is an input mask signal for write data. Input data is masked when

DM is sampled HIGH along with that input data during a WRITE access. DM is sampled

on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ

and DQS loading. For the x16, LDM corresponds to the data on DQ0-Q7; UDM corre-

sponds to the data on DQ8-Q15.

Data Strobe: Output with read data, input with write data. Edge aligned with read data,

centered in write data. Used to capture write data. For the x16, LDQS corresponds to the

data on DQ0-Q7; UDQS corresponds to the data on DQ8-Q15.

Data input / output pin : Data bus

Power supply for internal circuits and input buffers.

Power supply for output buffers for noise immunity.

Reference voltage for inputs for SSTL interface.

No connection.

CKE

Input

/CS

Input

BA0, BA1

Input

A0 ~ A12

Input

/RAS, /CAS, /WE

Input

(LDM, UDM)

Input

DQS

(LDQS, UDQS)

DDQ

SSQ

REF

I/O

Supply

Rev. 0.3 / Oct. 2003

HY5DU561622CT-D相似产品对比

	HY5DU561622CT-D	HY5DU56422CT-D43	HY5DU56822CT-D43	HY5DU56422CT-D4	HY5DU56822CT-D4	HY5DU56822CT-D	HY5DU56422CT-D	HY5DU561622CT-D43	HY5DU561622CT-D4
描述	256M-P DDR SDRAM	256M-P DDR SDRAM	256M-P DDR SDRAM	256M-P DDR SDRAM	256M-P DDR SDRAM	256M-P DDR SDRAM	256M-P DDR SDRAM	256M-P DDR SDRAM	256M-P DDR SDRAM
是否Rohs认证	-	不符合	不符合	不符合	不符合	-	-	不符合	不符合
厂商名称	-	SK Hynix(海力士)	SK Hynix(海力士)	SK Hynix(海力士)	SK Hynix(海力士)	-	-	SK Hynix(海力士)	SK Hynix(海力士)
零件包装代码	-	TSOP2	TSOP2	TSOP2	TSOP2	-	-	TSOP2	TSOP2
包装说明	-	TSOP2, TSSOP66,.46	TSOP2, TSSOP66,.46	TSOP2, TSSOP66,.46	TSOP2, TSSOP66,.46	-	-	TSOP2, TSSOP66,.46	TSOP2, TSSOP66,.46
针数	-	66	66	66	66	-	-	66	66
Reach Compliance Code	-	compliant	compliant	compli	compliant	-	-	compli	compli
ECCN代码	-	EAR99	EAR99	EAR99	EAR99	-	-	EAR99	EAR99
访问模式	-	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	-	-	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
最长访问时间	-	0.65 ns	0.65 ns	0.65 ns	0.65 ns	-	-	0.65 ns	0.65 ns
其他特性	-	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	-	-	AUTO/SELF REFRESH	AUTO/SELF REFRESH
最大时钟频率 (fCLK)	-	200 MHz	200 MHz	200 MHz	200 MHz	-	-	200 MHz	200 MHz
I/O 类型	-	COMMON	COMMON	COMMON	COMMON	-	-	COMMON	COMMON
交错的突发长度	-	2,4,8	2,4,8	2,4,8	2,4,8	-	-	2,4,8	2,4,8
JESD-30 代码	-	R-PDSO-G66	R-PDSO-G66	R-PDSO-G66	R-PDSO-G66	-	-	R-PDSO-G66	R-PDSO-G66
长度	-	22.22 mm	22.22 mm	22.22 mm	22.22 mm	-	-	22.22 mm	22.22 mm
内存密度	-	268435456 bit	268435456 bit	268435456 bi	268435456 bit	-	-	268435456 bi	268435456 bi
内存集成电路类型	-	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	-	-	DDR DRAM	DDR DRAM
内存宽度	-	4	8	4	8	-	-	16	16
功能数量	-	1	1	1	1	-	-	1	1
端口数量	-	1	1	1	1	-	-	1	1
端子数量	-	66	66	66	66	-	-	66	66
字数	-	67108864 words	33554432 words	67108864 words	33554432 words	-	-	16777216 words	16777216 words
字数代码	-	64000000	32000000	64000000	32000000	-	-	16000000	16000000
工作模式	-	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	-	-	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	-	70 °C	70 °C	70 °C	70 °C	-	-	70 °C	70 °C
组织	-	64MX4	32MX8	64MX4	32MX8	-	-	16MX16	16MX16
输出特性	-	3-STATE	3-STATE	3-STATE	3-STATE	-	-	3-STATE	3-STATE
封装主体材料	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-	-	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	-	TSOP2	TSOP2	TSOP2	TSOP2	-	-	TSOP2	TSOP2
封装等效代码	-	TSSOP66,.46	TSSOP66,.46	TSSOP66,.46	TSSOP66,.46	-	-	TSSOP66,.46	TSSOP66,.46
封装形状	-	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	-	-	RECTANGULAR	RECTANGULAR
封装形式	-	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	-	-	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE
峰值回流温度（摄氏度）	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-	-	NOT SPECIFIED	NOT SPECIFIED
电源	-	2.6 V	2.6 V	2.6 V	2.6 V	-	-	2.6 V	2.6 V
认证状态	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified	-	-	Not Qualified	Not Qualified
刷新周期	-	8192	8192	8192	8192	-	-	8192	8192
座面最大高度	-	1.194 mm	1.194 mm	1.194 mm	1.194 mm	-	-	1.194 mm	1.194 mm
自我刷新	-	YES	YES	YES	YES	-	-	YES	YES
连续突发长度	-	2,4,8	2,4,8	2,4,8	2,4,8	-	-	2,4,8	2,4,8
最大待机电流	-	0.01 A	0.01 A	0.01 A	0.01 A	-	-	0.01 A	0.01 A
最大压摆率	-	0.3 mA	0.3 mA	0.3 mA	0.3 mA	-	-	0.32 mA	0.32 mA
最大供电电压 (Vsup)	-	2.7 V	2.7 V	2.7 V	2.7 V	-	-	2.7 V	2.7 V
最小供电电压 (Vsup)	-	2.5 V	2.5 V	2.5 V	2.5 V	-	-	2.5 V	2.5 V
标称供电电压 (Vsup)	-	2.6 V	2.6 V	2.6 V	2.6 V	-	-	2.6 V	2.6 V
表面贴装	-	YES	YES	YES	YES	-	-	YES	YES
技术	-	CMOS	CMOS	CMOS	CMOS	-	-	CMOS	CMOS
温度等级	-	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	-	-	COMMERCIAL	COMMERCIAL
端子形式	-	GULL WING	GULL WING	GULL WING	GULL WING	-	-	GULL WING	GULL WING
端子节距	-	0.65 mm	0.65 mm	0.65 mm	0.65 mm	-	-	0.65 mm	0.65 mm
端子位置	-	DUAL	DUAL	DUAL	DUAL	-	-	DUAL	DUAL
处于峰值回流温度下的最长时间	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-	-	NOT SPECIFIED	NOT SPECIFIED
宽度	-	10.16 mm	10.16 mm	10.16 mm	10.16 mm	-	-	10.16 mm	10.16 mm

HY5DU561622CT-D

HY5DU561622CT-D概述

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