HY5PS1G431(L)F
HY5PS1G831(L)F
1Gb DDR2 SDRAM
HY5PS1G431(L)F
HY5PS1G831(L)F
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.2 / Dec 2006
1
1HY5PS1G431(L)F
1HY5PS1G831(L)F
Revision History
Rev.
0.1
0.2
Preliminary
Corrected typos of Pin description & tRFC spec. ,
Added IDD spec.
Editorial Clean up, Transfered Functional description, command truth table pages and
Some contents of Operating conditions to <Device Operation & timing diagram>
Updated IDD spec.
1.1
1.2
Corrected typo, and removed improper note in ODT DC spec.
Corrected Pinout Numbering
History
Draft Date
Feb.2004
Apr.2004
Jul. 2004
Feb. 2005
July 2006
Dec 2006
1.0
Rev. 1.2 / Dec 2006
2
1HY5PS1G431(L)F
1HY5PS1G831(L)F
Contents
1. Description
1.1 Device Features and Ordering Information
1.1.1 Key Feaures
1.1.2 Ordering Information
1.1.3 Ordering Frequency
1.2 Pin configuration
1.3 Pin Description
2. Maximum DC ratings
2.1 Absolute Maximum DC Ratings
2.2 Operating Temperature Condition
3. AC & DC Operating Conditions
3.1 DC Operating Conditions
5.1.1 Recommended DC Operating Conditions(SSTL_1.8)
5.1.2 ODT DC Electrical Characteristics
3.2 DC & AC Logic Input Levels
3.2.1 Input DC Logic Level
3.2.2 Input AC Logic Level
3.2.3 AC Input Test Conditions
3.2.4 Differential Input AC Logic Level
3.2.5 Differential AC output parameters
3.3 Output Buffer Levels
3.3.1 Output AC Test Conditions
3.3.2 Output DC Current Drive
3.3.3 OCD default chracteristics
3.4 IDD Specifications & Measurement Conditions
3.5 Input/Output Capacitance
4. AC Timing Specifications
5. Package Dimensions
Rev. 1.2 / Dec 2006
3
1HY5PS1G431(L)F
1HY5PS1G831(L)F
1. Description
1.1 Device Features & Ordering Information
1.1.1 Key Features
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VDD=1.8V
VDDQ=1.8V +/- 0.1V
All inputs and outputs are compatible with SSTL_18 interface
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS)
Differential Data Strobe (DQS, DQS)
Data outputs on DQS, DQS edges when read (edged DQ)
Data inputs on DQS centers when write(centered DQ)
On chip DLL align DQ, DQS and DQS transition with CK transition
DM mask write data-in at the both rising and falling edges of the data strobe
All addresses and control inputs except data, data strobes and data masks latched on the rising
edges of the clock
Programmable CAS latency 3, 4, 5 and 6 supported
Programmable additive latency 0, 1, 2, 3, 4 and 5 supported
Programmable burst length 4/8 with both nibble sequential and interleave mode
Internal eight bank operations with single pulsed RAS
Auto refresh and self refresh supported
tRAS lockout supported
8K refresh cycles /64ms
JEDEC standard 68ball FBGA(x4/x8)
Full strength driver option controlled by EMRS
On Die Termination supported
Off Chip Driver Impedance Adjustment supported
Read Data Strobe suupported (x8 only)
Self-Refresh High Temperature Entry
Ordering Information
Part No.
HY5PS1G431(L)F-X*
HY5PS1G831(L)F-X*
Configuration Package
256Mx4
128Mx8
68Ball
Operating Frequency
Grade
-E3
-E4
-C4
-C5
tCK(ns)
5
5
3.75
3.75
3
3
CL
3
4
4
5
5
6
tRCD
3
4
4
5
5
6
tRP
3
4
4
5
5
6
Unit
Clk
Clk
Clk
Clk
Clk
Clk
Note:
-X* is the speed bin, refer to the Operation
Frequency table for complete Part No.
-Y5
-Y6
Rev. 1.2 / Dec 2006
4
1HY5PS1G431(L)F
1HY5PS1G831(L)F
1.2 Pin Configuration & Address Table
256Mx4 DDR2 Pin Configuration
1
NC
2
NC
3
A
B
C
D
7
8
NC
9
NC
VDD
NC
VDDQ
NC
VDDL
NC
VSSQ
DQ1
VSSQ
VREF
CKE
VSS
DM
VDDQ
DQ3
VSS
WE
BA1
A1
A5
A9
NC
E
F
G
H
J
K
L
M
N
P
R
T
U
V
VSSQ
DQS
VDDQ
DQ2
VSSDL
RAS
CAS
A2
A6
A11
NC
DQS
VSSQ
DQ0
VSSQ
CK
CK
CS
A0
A4
A8
A13
VDDQ
NC
VDDQ
NC
VDD
ODT
BA2
BA0
A10
VDD
VSS
A3
A7
VSS
VDD
A12
NC
NC
W
NC
NC
ROW AND COLUMN ADDRESS TABLE
ITEMS
# of Bank
Bank Address
Auto Precharge Flag
Row Address
Column Address
Page size
256Mx4
8
BA0,BA1,BA2
A10/AP
A0 - A13
A0-A9, A11
1 KB
Rev. 1.2 / Dec 2006
5
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