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HY5S6B6DLFP-BE: 产品描述4Banks x1M x 16bits Synchronous DRAM; 产品类别存储存储; 文件大小357KB，共27页; 制造商SK Hynix(海力士); 官网地址http://www.hynix.com/eng/

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HY5S6B6DLFP-BE概述

4Banks x1M x 16bits Synchronous DRAM

HY5S6B6DLFP-BE规格参数

参数名称	属性值
厂商名称	SK Hynix(海力士)
零件包装代码	BGA
包装说明	TFBGA, BGA54,9X9,32
针数	54
Reach Compliance Code	unknow
ECCN代码	EAR99
访问模式	FOUR BANK PAGE BURST
最长访问时间	9 ns
其他特性	AUTO/SELF REFRESH
最大时钟频率 (fCLK)	67 MHz
I/O 类型	COMMON
交错的突发长度	1,2,4,8
JESD-30 代码	S-PBGA-B54
JESD-609代码	e1
长度	8 mm
内存密度	67108864 bi
内存集成电路类型	SYNCHRONOUS DRAM
内存宽度	16
功能数量	1
端口数量	1
端子数量	54
字数	4194304 words
字数代码	4000000
工作模式	SYNCHRONOUS
最高工作温度	85 °C
最低工作温度	-25 °C
组织	4MX16
输出特性	3-STATE
封装主体材料	PLASTIC/EPOXY
封装代码	TFBGA
封装等效代码	BGA54,9X9,32
封装形状	SQUARE
封装形式	GRID ARRAY, THIN PROFILE, FINE PITCH
电源	1.8 V
认证状态	Not Qualified
刷新周期	4096
座面最大高度	1.2 mm
自我刷新	YES
连续突发长度	1,2,4,8,FP
最大待机电流	0.0003 A
最大压摆率	0.06 mA
最大供电电压 (Vsup)	1.95 V
最小供电电压 (Vsup)	1.65 V
标称供电电压 (Vsup)	1.8 V
表面贴装	YES
技术	CMOS
温度等级	OTHER
端子面层	TIN SILVER COPPER
端子形式	BALL
端子节距	0.8 mm
端子位置	BOTTOM
宽度	8 mm

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HY5S6B6D(L/S)F(P)-xE

4Banks x1M x 16bits Synchronous DRAM

Document Title

4Bank x 1M x 16bits Synchronous DRAM

Revision History

Revision No.

0.1

0.2

0.3

Initial Draft

Append Super-Low Power Group to the Data-sheet

Changed DC Characteristics

Changed Package Information

History

Draft Date

Sep. 2003

Oct. 2003

Nov. 2003

July 2004

Remark

Preliminary

This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for

use of circuits described. No patent licenses are implied.

Rev 0.3 / July 2004

HY5S6B6D(L/S)F(P)-xE

4Banks x1M x 16bits Synchronous DRAM

DESCRIPTION

The Hynix Low Power SDRAM is suited for non-PC application which use the batteries such as PDAs, 2.5G and 3G cellular

phones with internet access and multimedia capabilities, mini-notebook, handheld PCs.

The Hynix HY5S6B6D(L/S)F(P) is a 67,108,864bit CMOS Synchronous Dynamic Random Access Memory. It is organized

as 4banks of 1,048,576x16.

The Low Power SDRAM provides for programmable options including CAS latency of 1, 2, or 3, READ or WRITE burst

length of 1, 2, 4, 8, or full page, and the burst count sequence(sequential or interleave). And the Low Power SDRAM

also provides for special programmable options including Partial Array Self Refresh of a quarter bank, a half bank,

1bank, 2banks, or all banks.

The Hynix HY5S6B6D(L/S)F(P) has the special Low Power function of Auto TCSR(Temperature Compensated Self Re-

fresh) to reduce self refresh current consumption. Since an internal temperature sensor is implanted, it enables to au-

tomatically adjust refresh rate according to temperature without external EMRS command. A burst of Read or Write

cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst

Read or Write command on any cycle(This pipelined design is not restricted by a 2N rule).

Deep Power Down Mode is a additional operating mode for Low Power SDRAM. This mode can achieve maximum power

reduction by removing power to the memory array within each SDRAM. By using this feature, the system can cut off

alomost all DRAM power without adding the cost of a power switch and giving up mother-board power-line layout

flexibility.

FEATURES

Standard SDRAM Protocol

nternal 4bank operation

●

Power Supply Voltage : VDD = 1.8V, VDDQ = 1.8V

LVCMOS compatible I/O Interface

Low Voltage interface to reduce I/O power

Low Power Features

- PASR(Partial Array Self Refresh)

- AUTO TCSR (Temperature Compensated Self Refresh)

- DS (Drive Strength)

- Deep Power Down Mode

Programmable CAS latency of 1, 2 or 3

Package Type : 54ball, 0.8mm pitch FBGA (Lead Free, Lead)

HY5S6B6D(L/S)FP : Lead Free

HY5S6B6D(L/S)F : Lead

●

ORDERING INFORMATION

Part Number

HY5S6B6D(L/S)F(P)-SE

HY5S6B6D(L/S)F(P)-BE

Clock Frequency

105MHz

66MHz

CAS

Latency

4banks x 1Mb x 16

LVCMOS

Organization

Interface

This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for

use of circuits described. No patent licenses are implied.

Rev 0.3 / July 2004

HY5S6B6DLFP-BE相似产品对比

	HY5S6B6DLFP-BE	HY5S6B6D	HY5S6B6DLF-BE	HY5S6B6DLF-SE	HY5S6B6DLFP-SE	HY5S6B6DSFP-BE	HY5S6B6DSF-BE
描述	4Banks x1M x 16bits Synchronous DRAM	4Banks x1M x 16bits Synchronous DRAM	4Banks x1M x 16bits Synchronous DRAM	4Banks x1M x 16bits Synchronous DRAM	4Banks x1M x 16bits Synchronous DRAM	4Banks x1M x 16bits Synchronous DRAM	4Banks x1M x 16bits Synchronous DRAM
厂商名称	SK Hynix(海力士)	-	SK Hynix(海力士)	SK Hynix(海力士)	SK Hynix(海力士)	SK Hynix(海力士)	SK Hynix(海力士)
零件包装代码	BGA	-	BGA	BGA	BGA	BGA	BGA
包装说明	TFBGA, BGA54,9X9,32	-	TFBGA, BGA54,9X9,32	TFBGA, BGA54,9X9,32	TFBGA, BGA54,9X9,32	TFBGA, BGA54,9X9,32	TFBGA, BGA54,9X9,32
针数	54	-	54	54	54	54	54
Reach Compliance Code	unknow	-	unknown	unknow	unknown	unknow	unknown
ECCN代码	EAR99	-	EAR99	EAR99	EAR99	EAR99	EAR99
访问模式	FOUR BANK PAGE BURST	-	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
最长访问时间	9 ns	-	9 ns	7 ns	7 ns	9 ns	9 ns
其他特性	AUTO/SELF REFRESH	-	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
最大时钟频率 (fCLK)	67 MHz	-	67 MHz	105 MHz	105 MHz	67 MHz	67 MHz
I/O 类型	COMMON	-	COMMON	COMMON	COMMON	COMMON	COMMON
交错的突发长度	1,2,4,8	-	1,2,4,8	1,2,4,8	1,2,4,8	1,2,4,8	1,2,4,8
JESD-30 代码	S-PBGA-B54	-	S-PBGA-B54	S-PBGA-B54	S-PBGA-B54	S-PBGA-B54	S-PBGA-B54
JESD-609代码	e1	-	e1	e1	e1	e1	e1
长度	8 mm	-	8 mm	8 mm	8 mm	8 mm	8 mm
内存密度	67108864 bi	-	67108864 bit	67108864 bi	67108864 bit	67108864 bi	67108864 bit
内存集成电路类型	SYNCHRONOUS DRAM	-	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM
内存宽度	16	-	16	16	16	16	16
功能数量	1	-	1	1	1	1	1
端口数量	1	-	1	1	1	1	1
端子数量	54	-	54	54	54	54	54
字数	4194304 words	-	4194304 words	4194304 words	4194304 words	4194304 words	4194304 words
字数代码	4000000	-	4000000	4000000	4000000	4000000	4000000
工作模式	SYNCHRONOUS	-	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	85 °C	-	85 °C	85 °C	85 °C	85 °C	85 °C
最低工作温度	-25 °C	-	-25 °C	-25 °C	-25 °C	-25 °C	-25 °C
组织	4MX16	-	4MX16	4MX16	4MX16	4MX16	4MX16
输出特性	3-STATE	-	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
封装主体材料	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	TFBGA	-	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA
封装等效代码	BGA54,9X9,32	-	BGA54,9X9,32	BGA54,9X9,32	BGA54,9X9,32	BGA54,9X9,32	BGA54,9X9,32
封装形状	SQUARE	-	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
封装形式	GRID ARRAY, THIN PROFILE, FINE PITCH	-	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH
电源	1.8 V	-	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
认证状态	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
刷新周期	4096	-	4096	4096	4096	4096	4096
座面最大高度	1.2 mm	-	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm
自我刷新	YES	-	YES	YES	YES	YES	YES
连续突发长度	1,2,4,8,FP	-	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP
最大待机电流	0.0003 A	-	0.0003 A	0.0003 A	0.0003 A	0.0003 A	0.0003 A
最大压摆率	0.06 mA	-	0.06 mA	0.08 mA	0.08 mA	0.06 mA	0.06 mA
最大供电电压 (Vsup)	1.95 V	-	1.95 V	1.95 V	1.95 V	1.95 V	1.95 V
最小供电电压 (Vsup)	1.65 V	-	1.65 V	1.65 V	1.65 V	1.65 V	1.65 V
标称供电电压 (Vsup)	1.8 V	-	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
表面贴装	YES	-	YES	YES	YES	YES	YES
技术	CMOS	-	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	OTHER	-	OTHER	OTHER	OTHER	OTHER	OTHER
端子面层	TIN SILVER COPPER	-	TIN SILVER COPPER	TIN SILVER COPPER	TIN SILVER COPPER	TIN SILVER COPPER	TIN SILVER COPPER
端子形式	BALL	-	BALL	BALL	BALL	BALL	BALL
端子节距	0.8 mm	-	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm
端子位置	BOTTOM	-	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
宽度	8 mm	-	8 mm	8 mm	8 mm	8 mm	8 mm

HY5S6B6DLFP-BE

HY5S6B6DLFP-BE概述

HY5S6B6DLFP-BE规格参数

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