HY62LF16806B Series
512Kx16bit full CMOS SRAM
Document Title
512K x16 bit 2.5V Super Low Power Full CMOS slow SRAM
Revision History
Revision No
00
History
Initial Draft
Draft Date
May.29.2001
Remark
Preliminary
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.00 /May. 2001
Hynix Semiconductor
HY62LF16806B Series
Preliminary
DESCRIPTION
The HY62LF16806B is a high speed, super low
power and 8Mbit full CMOS SRAM organized as
524,288 words by 16bits. The HY62LF16806B
uses high performance full CMOS process
technology and is designed for high speed and
low power circuit technology. It is particularly well-
suited for the high density low power system
application. This device has a data retention
mode that guarantees data to remain valid at a
minimum power supply voltage of 1.2V.
Product
Voltage
Speed
No.
(V)
(ns)
HY62LF16806B-C
2.3~2.7 70/85/100
HY62LF16806B- I
2.3~2.7 70/85/100
Note 1. C : Commercial, I : Industrial
2. Current value is max.
FEATURES
•
Fully static operation and Tri-state output
•
TTL compatible inputs and outputs
•
Battery backup(LL/SL-part)
- 1.2V(min) data retention
•
Standard pin configuration
- 48-FBGA
Operation
Current/Icc(mA)
3
3
Standby Current(uA)
LL
SL
20
8
20
8
Temperature
(°C)
0~70
-45~85
PIN CONNECTION
( Top View )
1
2
/OE
/UB
3
A0
A3
4
A1
A4
A6
A7
A16
A15
A13
A10
5
A2
/CS1
IO2
IO4
IO5
IO6
6
CS2
IO1
ADD INPUT
BUFFER
BLOCK DIAGRAM
ROW
DECODER
SENSE AMP
A
B
C
D
E
F
G
H
/LB
IO9
I/O1
COLUMN
DECODER
I/O8
DATA I/O
BUFFER
PRE DECODER
IO10 IO11 A5
Vss
Vcc
IO12 A17
IO13 Vss
IO3
Vcc
Vss
IO7
A18
MEMORY ARRAY
512K x 16
WRITE DRIVER
I/O9
BLOCK
DECODER
IO15 IO14 A14
IO16 NC
A18
A8
A12
A9
I/O16
/WE IO8
A11
NC
/CS1
CS2
/OE
/LB
/UB
/WE
PIN DESCRIPTION
Pin Name
/CS1, CS2
/WE
/OE
/LB
/UB
Pin Function
Chip Select
Write Enable
Output Enable
Lower Byte Control(I/O1~I/O8)
Upper Byte Control(I/O9~I/O16)
Pin Name
I/O1~I/O16
A0~A18
Vcc
Vss
NC
Pin Function
Data Inputs / Outputs
Address Inputs
Power(2.3V~2.7V)
Ground
No Connection
Rev.00/May. 2001
2
HY62LF16806B Series
ORDERING INFORMATION
Part No.
Speed
HY62LF16806B-DFC
70/85/100
HY62LF16806B-SFC
70/85/100
HY62LF16806B-DFI
70/85/100
HY62LF16806B-SFI
70/85/100
Note 1. C : Commercial, I : Industrial
Power
LL-part
SL-part
LL-part
SL-part
Package
FBGA
FBGA
FBGA
FBGA
Temp.
C
C
I
I
ABSOLUTE MAXIMUM RATINGS (1)
Symbol
V
IN,
V
OUT
Vcc
T
A
T
STG
P
D
T
SOLDER
Parameter
Input/Output Voltage
Power Supply
Operating Temperature
Storage Temperature
Power Dissipation
Ball Soldering Temperature & Time
Rating
-0.3 to Vcc+0.3
-0.3 to 3.6
0 to 70
-40 to 85
-55 to 150
1.0
260
•
10
Unit
V
V
°C
°C
°C
W
°C •
sec
Remark
HY62LF16806B-C
HY62LF16806B-I
Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied.
Exposure to the absolute maximum rating conditions for extended period may affect reliability.
TRUTH TABLE
/CS1
H
X
X
L
L
L
CS2
X
L
X
H
H
H
/WE
X
X
X
H
H
H
/OE
X
X
X
H
H
L
/LB
X
X
H
L
X
L
H
L
L
H
L
/UB
X
X
H
X
L
H
L
L
H
L
L
Mode
Deselected
Output Disabled
Read
L
H
L
X
Write
I/O Pin
I/O1~I/O8
I/O9~I/O16
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
D
OUT
Hi-Z
Hi-Z
D
OUT
D
OUT
D
OUT
D
IN
Hi-Z
Hi-Z
D
IN
D
IN
D
IN
Power
Standby
Active
Active
Active
Note:
1. H=V
IH
, L=V
IL
, X=don't care(V
IH or
V
IL)
2. UB, LB(Upper, Lower Byte enable)
These active LOW inputs allow individual bytes to be written or read.
When LB is LOW, data is written or read to the lower byte, I/O1 -I/O8.
When UB is LOW, data is written or read to the upper byte, I/O9 -I/O16.
Rev.00/May. 2001
2
HY62LF16806B Series
RECOMMENDED DC OPERATING CONDITION
Symbol
Vcc
Vss
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
2.3
0
2.0
-0.3
(1)
Typ.
2.5
0
-
-
Max.
2.7
0
Vcc+0.3
0.6
Unit
V
V
V
V
Note : 1. VIL = -1.5V for pulse width less than 30ns
DC ELECTRICAL CHARACTERISTICS
Vcc = 2.3V~2.7V, T
A
= 0°C to 70°C / -40°C to 85°C
Sym
Parameter
Test Condition
I
LI
Input Leakage Current
Vss < V
IN
< Vcc
Vss < V
OUT
< Vcc,
/CS1 = V
IH
or CS2=V
IL
or
I
LO
Output Leakage Current
/
OE
=
V
IH
or /WE = V
IL
or
/
UB
=
V
IH ,
/LB = V
IH
/CS1 = V
IL
, CS2=V
IH
,
Icc
Operating Power Supply Current
V
IN
= V
IH
or V
IL,
I
I/O =
0mA
/CS1 = V
IL,
CS2 = V
IH
,
V
IN
= V
IH
or V
IL,
Cycle Time = Min,
100% Duty, I
I/O =
0mA
I
CC1
Average Operating Current
/CS1 < 0.2V
,
CS2 > Vcc-0.2V,
V
IN
< 0.2V or V
IN
> Vcc-0.2V
,
Cycle Time = 1us,
100% Duty, I
I/O =
0mA
/CS1 = V
IH
or CS2 = V
IL
or
I
SB
Standby Current
(TTL Input)
/UB, /LB = V
IH
V
IN
= V
IH
or V
IL
/CS1 > Vcc - 0.2V or
SL
CS2 < Vss + 0.2V or
I
SB1
Standby Current
(CMOS Input)
/UB, /LB > Vcc - 0.2V
LL
V
IN
> Vcc - 0.2V or
V
IN
< Vss + 0.2V
V
OL
Output Low
I
OL
= 0.5mA
V
OH
Output High
I
OH =
-0.5mA
Note :
1. Typical values are at Vcc = 2.5V, T
A
= 25°C
2. Typical values are not 100% tested
Min
-1
-1
Typ
1.
-
-
Max
1
1
Unit
uA
uA
3
30
mA
mA
5
mA
0.1
mA
-
1
8
20
uA
uA
-
2.0
-
-
0.4
-
V
V
CAPACITANCE
(Temp = 25°C, f = 1.0MHz)
Symbol
Parameter
C
IN
Input Capacitance (Add, /CS1,CS2,/LB,/UB, /WE, /OE)
C
OUT
Output Capacitance (I/O)
Note : These parameters are sampled and not 100% tested
Condition
V
IN
= 0V
V
I/O
= 0V
Max.
8
10
Unit
pF
pF
Rev.00/May. 2001
3
HY62LF16806B Series
AC CHARACTERISTICS
Vcc = 2.3V~2.7V, T
A
= 0°C to 70°C/ -40°C to 85°C, unless otherwise specified
-70
-85
#
Symbol Parameter
Min.
Max. Min.
Max.
READ CYCLE
1
tRC
Read Cycle Time
70
-
85
-
2
tAA
Address Access Time
-
70
-
85
3
tACS
Chip Select Access Time
-
70
-
85
4
tOE
Output Enable to Output Valid
-
35
-
40
5
tBA
/LB, /UB Access Time
-
70
-
85
6
tCLZ
Chip Select to Output in Low Z
10
-
10
-
7
tOLZ
Output Enable to Output in Low Z
5
-
5
-
8
tBLZ
/LB, /UB Enable to Output in Low Z
10
-
10
-
9
tCHZ
Chip Deselection to Output in High Z
0
30
0
30
10 tOHZ
Out Disable to Output in High Z
0
30
0
30
11 tBHZ
/LB, /UB Disable to Output in High Z
0
30
0
30
12 tOH
Output Hold from Address Change
10
-
10
-
WRITE CYCLE
13 tWC
Write Cycle Time
70
-
85
-
14 tCW
Chip Selection to End of Write
60
-
70
-
15 tAW
Address Valid to End of Write
60
-
70
-
16 tBW
/LB, /UB Valid to End of Write
60
-
70
-
17 tAS
Address Set-up Time
0
-
0
-
18 tWP
Write Pulse Width
50
-
60
-
19 tWR
Write Recovery Time
0
-
0
-
20 tWHZ
Write to Output in High Z
0
20
0
25
21 tDW
Data to Write Time Overlap
30
-
35
-
22 tDH
Data Hold from Write Time
0
-
0
-
23 tOW
Output Active from End of Write
5
-
5
-
-10
Min
Max.
100
-
-
-
-
10
5
10
0
0
0
15
100
80
80
80
0
70
0
0
45
0
10
-
100
100
45
100
-
-
-
30
30
30
-
-
-
-
-
-
-
-
25
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AC TEST CONDITIONS
T
A
= 0°C to 70°C(Commercial)/ -40°C to 85°C, unless otherwise specified
PARAMETER
Input Pulse Level
Input Rise and Fall Time
Input and Output Timing Reference Level
tCLZ,tOLZ,tBLZ,tCHZ,tOHZ,tBHZ,tWHZ,tOW
Output Load
Other
Value
0.4V to 2.2V
5ns
1.1V
CL = 5pF + 1TTL Load
CL = 30pF + 1TTL Load
AC TEST LOADS
V
TM
= 2.3V
3067 Ohm
D
OUT
CL(1)
3345 Ohm
Note
1. Including jig and scope capacitance
Rev.00/May. 2001
4
FPGA/CPLD
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