January 2007
HYS72T256023HR–5–A
H Y S7 2T 5 1 2022H R– 3 S– A
HYS72T512022HR–3.7–A
HYS72T512022HR–5–A
240-Pin Registered DDR2 SDRAM Modules
DDR2 SDRAM
RDIMM SDRAM
RoHS compliant
Internet Data Sheet
Rev. 1.2
Internet Data Sheet
HYS72T[512/256]02xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
HYS72T256023HR–5–A, HYS72T512022HR–3S–A, HYS72T512022HR–3.7–A, HYS72T512022HR–5–A
Revision History: 2007-01, Rev. 1.2
Page
All
All
All
33, 35
40
Subjects (major changes since last revision)
Adapted internet edition
Updated for Product Types HYS72T512022HR–3S–A and HYS72T256023HR–5–A
Qimonda update
SPD Update
Package outline figure update
Previous Revision: 2005-09, Rev. 1.11
Previous Revision: 2005-08, Rev. 1.1
Previous Revision: 2005-05, Rev. 1.0
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
techdoc@qimonda.com
qag_techdoc_rev400 / 3.2 QAG / 2006-08-07
03292006-AYVF-ZIIJ
2
Internet Data Sheet
HYS72T[512/256]02xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
1
Overview
This chapter gives an overview of the 240-pin Registered DDR2 SDRAM Modules product family and describes its main
characteristics.
1.1
Features
• Auto Refresh (CBR) and Self Refresh
• Average Refresh Period 7.8
µs
at a
T
CASE
lower than
85 °C, 3.9µs between 85 °C and 95
°C.
• All inputs and outputs SSTL_1.8 compatible
• Off-Chip Driver Impedance Adjustment (OCD) and On-Die
Termination (ODT)
• Serial Presence Detect with E
2
PROM
• RDIMM Dimensions (nominal): 30 mm high, 133.35 mm
wide
• Based on standard reference layouts Raw Card “D” and
“Z“
• RoHS compliant products
1)
• 240-pin PC2–5300, PC2-4200 and PC2-3200 DDR2
SDRAM memory modules Workstation and Server main
memory applications
• Two rank 256M
×
72, 512M
×
72 module organization and
2
×
128M
×
8, 2
×
256M
×
4 chip organization
• 2GByte, 4 GByte module built with stacked 1-Gbit DDR2
SDRAMs in P-TFBGA-71 chipsize packages
• Standard DDR2 Synchronous DRAMs (DDR2 SDRAM)
with a single + 1.8 V (± 0.1 V) power supply
• All Speed grades faster than DDR2-400 can operate with
DDR2-400 timing specifications aswell
• Programmable CAS Latencies (3, 4 & 5),
Burst Length (4 & 8) and Burst Type
TABLE 1
Performance Table
Product Type Speed Code
Speed Grade
Max. Clock Frequency
@CL5
@CL4
@CL3
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
–3S
PC2–5300
5–5–5
–3.7
PC2–4200
4–4–4
266
266
200
15
15
45
60
–5
PC2–3200
4–4–4
200
200
200
15
15
40
55
Unit
—
MHz
MHz
MHz
ns
ns
ns
ns
f
CK5
f
CK4
f
CK3
t
RCD
t
RP
t
RAS
t
RC
333
266
200
15
15
45
60
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.2, 2007-01
03292006-AYVF-ZIIJ
3
Internet Data Sheet
HYS72T[512/256]02xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
1.2
Description
capacitive loading to the system bus, but adds one cycle to
the SDRAM timing. Decoupling capacitors are mounted on
the PCB board. The DIMMs feature serial presence detect
based on a serial E
2
PROM device using the 2-pin I
2
C
protocol. The first 128 bytes are programmed with
configuration data and the second 128 bytes are available to
the customer.
The
QIMONDA
HYS72T[512/256]02xHR–[3S/3.7/5]–A
module family are Registered DIMM modules “RDIMMs” with
30 mm height based on DDR2 technology. DIMMs are
available as ECC modules in 256M
×
72 (2 GByte),
512M
×
72 (4 GByte) organization and density, intended for
mounting into 240-Pin connector sockets.
The memory array is designed with stacked 1-Gbit Double-
Data-Rate-Two (DDR2) Synchronous DRAMs. All control and
address signals are re-driven on the DIMM using register
devices and a PLL for the clock distribution. This reduces
TABLE 2
Ordering Information for RoHS Compliant Products
Product Type
1)
PC2–5300
HYS72T512022HR–3S–A
PC2–4200
HYS72T512022HR–3.7–A
PC2-3200
HYS72T256023HR–5–A
HYS72T512022HR–5–A
2 GB 2R×8 PC2–3200R–333–12–ZZ
4 GB 2R×4 PC2–3200R–333–12–D0
2 Ranks, ECC
2 Ranks, ECC
1 Gbit (×8)
1 Gbit (×4)
4 GB 2R×4 PC2–4200R–444–12–D0
2 Ranks, ECC
1 Gbit (×4)
4 GB 2R×4 PC2–5300R–555–12–D0
2 Ranks, ECC
1 Gbit (×4)
Compliance Code
2)
Description
SDRAM Technology
1) All Product Type numbers end with a place code, designating the silicon die revision. Example: HYS72T512022HR–3.7–A, indicating Rev.
“A” dies are used for DDR2 SDRAM components. For all QIMONDA DDR2 module and component nomenclature see
Chapter 6
of this
data sheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200R–444–12–D0”, where
4200R means Registered DIMM modules with 4.26 GB/sec Module Bandwidth and “444-11” means Column Address Strobe (CAS) latency
= 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.2 and produced
on the Raw Card “D”
TABLE 3
Address Format
DIMM
Density
2 GB
4 GB
Module
Organization
256M
×
72
512M
×
72
Memory
Ranks
2
2
ECC/
Non-ECC
ECC
ECC
# of
SDRAMs
2
×
9
2
×
18
# of row/bank/columns bits
14/3/10
14/3/11
Raw Card
Z
D
TABLE 4
Components on Modules
Product Type
HYS72T256023HR
HYS72T512022HR
DRAM Components
HYB18T2G802AF
HYB18T2G402AF
DRAM Density
2 Gbit
2 Gbit
DRAM Organization
2
×
128M
×
8
2
×
256M
×
4
Note
1)
1) For a detailed description of all available functions of the DRAM components on these modules see the component data sheet.
Rev. 1.2, 2007-01
03292006-AYVF-ZIIJ
4
Internet Data Sheet
HYS72T[512/256]02xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
2
2.1
Pin Configuration
Pin Configuration
and
Table 7
respectively. The pin numbering is depicted in
Figure 1.
This chapter contains the pin configuration.
The pin configuration of the Registered DDR2 SDRAM DIMM
is listed by function in
Table 5
(240 pins). The abbreviations
used in columns Pin and Buffer Type are explained in
Table 6
TABLE 5
Pin Configuration of RDIMM
Ball No.
Clock Signals
185
186
52
171
CK0
CK0
CKE0
CKE1
NC
Control Signals
193
76
S0
S1
NC
192
74
73
18
Address Signals
71
190
54
BA0
BA1
BA2
NC
I
I
I
I
SSTL
SSTL
SSTL
SSTL
Bank Address Bus 2
Greater than 512Mb DDR2 SDRAMS
Not Connected
Less than 1Gb DDR2 SDRAMS
Bank Address Bus 1:0
RAS
CAS
WE
RESET
I
I
NC
I
I
I
I
SSTL
SSTL
—
SSTL
SSTL
SSTL
CMOS
Register Reset
Chip Select Rank 1:0
Note: 2-Ranks module
Not Connected
Note: 1-Rank module
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
I
I
I
I
NC
SSTL
SSTL
SSTL
SSTL
—
Clock Enables 1:0
Note: 2-Ranks module
Not Connected
Note: 1-Rank module
Clock Signal CK0, Complementary Clock Signal CK0
Name
Pin
Type
Buffer
Type
Function
Rev. 1.2, 2007-01
03292006-AYVF-ZIIJ
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
