July 2007
HYS72T1G242EP–[25F/2.5]–C
HYS72T1G242EP–[3/3S/3.7]–C
240-Pin Dual Die Registered DDR2 SDRAM Modules
RDIMM SDRAM
RoHS Compliant
Internet Data Sheet
Rev. 1.0
Internet Data Sheet
HYS72T1G242EP–[25F/2.5/3/3S/3.7]–C
Registerd DDR2 SDRAM Module
HYS72T1G242EP–[25F/2.5]–C, HYS72T1G242EP–[3/3S/3.7]–C
Revision History: 2007-07, Rev. 1.0
Page
All
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Subjects (major changes since last revision)
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07242007-LR08-OZC0
2
Internet Data Sheet
HYS72T1G242EP–[25F/2.5/3/3S/3.7]–C
Registerd DDR2 SDRAM Module
1
Overview
This chapter gives an overview of the 1.8 V 240-Pin Dual Die Registered DDR2 SDRAM Modules with parity bit product family
and describes its main characteristics.
1.1
Features
•
•
•
•
•
•
•
•
•
•
Programmable self refresh rate via EMRS2 setting
Programmable partial array refresh via EMRS2 settings
DCC enabling via EMRS2 setting
All inputs and outputs SSTL_18 compatible
Off-Chip Driver Impedance Adjustment (OCD) and On-Die
Termination (ODT)
Serial Presence Detect with E
2
PROM
RDIMM Dimensions (nominal): 30 mm high, 133.35 mm
wide
Based on standard reference card layouts Raw Card “Z”
All speed grades faster than DDR2–400 comply with
DDR2–400 timing specifications.
RoHS compliant products
1)
• 240-Pin PC2–6400, PC2–5300 and PC2–4200 DDR2
SDRAM memory modules.
• 1024M
×72
module organization and 512M
×4
chip
organization
• Registered DIMM Parity bit for address and control bus
• 8 GByte modules built with stacked 2 Gbit (1Gbit Dual
Dies) DDR2 SDRAMs in P-TFBGA-63 chipsize packages.
• Standard Double-Data-Rate-Two Synchronous DRAMs
(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power
supply
• Programmable CAS Latencies (3, 4, 5, 6), Burst Length (4
& 8)
• Auto Refresh (CBR) and Self Refresh
TABLE 1
Performance Table
Product Type Speed Code
DRAM Speed Grade
Speed Grade
CAS-RCD-RP latencies
Max. Clock
Frequency
–25F
DDR2–800D
PC2–6400
5-5-5
–
400
266
200
12.5
12.5
45
57.5
–2.5
DDR2–800E
PC2–6400
6-6-6
400
333
266
200
15
15
45
60
–3
DDR2–667C
PC2–5300
4-4-4
–
333
333
200
12
12
45
57
–3S
–3.7
Unit
DDR2–667D DDR2–533C
PC2–5300
5-5-5
–
333
266
200
15
15
45
60
PC2–4200
4-4-4
–
266
266
200
15
15
45
60
t
CK
MHz
MHz
MHz
MHz
ns
ns
ns
ns
f
CK6
@CL5
f
CK5
@CL4
f
CK4
@CL3
f
CK3
Min. RAS-CAS-Delay
t
RCD
Min. Row Precharge Time
t
RP
t
RAS
Min. Row Active Time
Min. Row Cycle Time
t
RC
@CL6
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.0, 2007-07
07242007-LR08-OZC0
3
Internet Data Sheet
HYS72T1G242EP–[25F/2.5/3/3S/3.7]–C
Registerd DDR2 SDRAM Module
1.2
Description
distribution. This reduces capacitive loading to the system
bus, but adds one cycle to the SDRAM timing. Decoupling
capacitors are mounted on the PCB board. The DIMMs
feature serial presence detect based on a serial E2PROM
device using the 2-pin I2C protocol. The first 128 bytes are
programmed with configuration data and the second
128 bytes are available to the customer.
The Qimonda HYS72T1G242EP–[25F/2.5/3//3S/3.7]–C module
family are Registered DIMM (with parity) modules with 30 mm
height based on DDR2 technology.
DIMMs are available as ECC modules in 1024M
×
72 (8 GB)
organization and density, intended for mounting into 240-Pin
connector sockets.
The memory array is designed with stacked 2 Gbit (1Gbit
Dual Dies) Double-Data-Rate-Two (DDR2) Synchronous
DRAMs. All control and address signals are re-driven on the
DIMM using register devices and a PLL for the clock
TABLE 2
Ordering Information for RoHS Compliant Products
Product Type
1)
PC2–6400
HYS72T1G242EP-2.5-C
HYS72T1G242EP-25F-C
PC2–5300
HYS72T1G242EP-3-C
HYS72T1G242EP-3S-C
PC2–4200
HYS72T1G242EP-3.7-C
8GB 4Rx4 PC2-4200P-444-12-ZZ
4 Rank, ECC
1Gbit (× 4)
1) All Product Type number end with a place code, designating the silicon die revision. Example: HYS72T1G242EP-3.7-C, indicating Rev.
“C” dies are used for DDR2 SDRAM components. For all Qimonda DDR2 module and component nomenclature see
Chapter 6
of this data
sheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200P–444–12–ZZ”, where 4200P
means Registered DIMM modules (with Parity Bit) with 4.26 GB/sec Module Bandwidth and “444-12” means Column Address Strobe
(CAS) latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.2
and produced on the Raw Card “F”
Compliance Code
2)
Description
SDRAM
Technology
1Gbit (× 4)
1Gbit (× 4)
1Gbit (× 4)
1Gbit (× 4)
8GB 4Rx4 PC2-6400P-666-12-ZZ
8GB 4Rx4 PC2-6400P-555-12-ZZ
8GB 4Rx4 PC2-5300P-444-12-ZZ
8GB 4Rx4 PC2-5300P-555-12-ZZ
4 Rank, ECC
4 Rank, ECC
4 Rank, ECC
4 Rank, ECC
TABLE 3
Address Format
DIMM
Density
8 GByte
Module
Organization
1024M
×72
Memory
Ranks
4
ECC/
Non-ECC
ECC
# of SDRAMs # of row/bank/column
bits
36DDP
1)
14/3/11
Raw
Card
Z
1) DDP Dual Die Package
TABLE 4
Components on Modules
Product Type
1)
HYS72T1G242EP
DRAM Components
HYB18T2G402CF
DRAM Density
1 Gbit
DRAM Organization
2
×
512M
×
4
1) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
Rev. 1.0, 2007-07
07242007-LR08-OZC0
4
Internet Data Sheet
HYS72T1G242EP–[25F/2.5/3/3S/3.7]–C
Registerd DDR2 SDRAM Module
2
2.1
Pin Configuration and Block Diagrams
Pin Configuration
and
Table 7
respectively. The pin numbering is depicted in
Figure 1.
This chapter contains the pin configuration and block diagrams.
The pin configuration of the Registered DDR2 SDRAM DIMM
is listed by function in
Table 5
(240 pins). The abbreviations
used in columns Pin and Buffer Type are explained in
Table 6
TABLE 5
Pin Configuration of RDIMM
Pin No.
Clock Signals
185
186
CK0
CK0
I
I
SSTL
SSTL
Clock Signal CK0, Complementary Clock Signal CK0
The system clock inputs. All address and command lines are sampled
on the cross point of the rising edge of CK and the falling edge of CK.
A Delay Locked Loop (DLL) circuit is driven from the clock inputs and
output timing for read operations is synchronized to the input clock.
Clock Enables 1:0
Activates the DDR2 SDRAM CK signal when HIGH and deactivates
the CK signal when LOW. By deactivating the clocks, CKE0 initiates
the Power Down Mode or the Self Refresh Mode.
Note: 2-Ranks module
Not Connected
Note: 1-Rank module
Chip Select
Enables the associated DDR2 SDRAM command decoder when LOW
and disables the command decoder when HIGH. When the command
decoder is disabled, new commands are ignored but previous
operations continue.
Rank 0 is selected by S0
Rank 1 is selected by S1
The input signals also disable all outputs (except CKE and ODT) of the
register(s) on the DIMM when both inputs are high. When S is HIGH,
all register outputs (except CK, ODT and Chip select) remain in the
previous state.
Note: 2-Ranks module
Not Connected
Note: 1-Rank module
Name
Pin
Type
Buffer
Type
Function
52
171
CKE0
CKE1
I
I
SSTL
SSTL
NC
Control Signals
193
76
S0
S1
NC
—
I
I
SSTL
SSTL
NC
NC
—
Rev. 1.0, 2007-07
07242007-LR08-OZC0
5
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