May 2007
HY[B/I]18T512400B2[C/F](L)
HY[B/I]18T512800B2[C/F](L)
HY[B/I]18T512160B2[C/F](L)
512-Mbit Double-Data-Rate-Two SDRAM
DDR2 SDRAM
RoHS Compliant Products
Internet Data Sheet
Rev. 1.12
Internet Data Sheet
HY[B/I]18T512[40/80/16]0B2[C/F](L)
512-Mbit Double-Data-Rate-Two SDRAM
HY[B/I]18T512400B2[C/F](L), HY[B/I]18T512800B2[C/F](L), HY[B/I]18T512160B2[C/F](L)
Revision History: 2007-05, Rev. 1.12
Page
All
105
6
Subjects (major changes since last revision)
Adapted internet edition
Corrected table Idd specification
Corrected table 5, 6 in chapter 1
Added HYB18T512xx0B2C, HYI18T512xx0B2C, HYI18T512xx0B2F and HYB18T512xx0B2FL
111
Added tRFC and tREFI parameters in the AC timing tables for 667 and 800
Previous Revision: 2006-10, Rev. 1.0
Previous Revision: 2007-05, Rev. 1.11
Previous Revision: 2007-05, Rev. 1.1
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
techdoc@qimonda.com
qag_techdoc_rev400 / 3.2 QAG / 2006-08-07
10062006-YPTZ-CDR7
2
Internet Data Sheet
HY[B/I]18T512[40/80/16]0B2[C/F](L)
512-Mbit Double-Data-Rate-Two SDRAM
1
Overview
This chapter gives an overview of the 512-Mbit Double-Data-Rate-Two SDRAM product family and describes its main
characteristics.
1.1
Features
The 512-Mbit Double-Data-Rate-Two SDRAM offers the following key features:
• Off-Chip-Driver impedance adjustment (OCD) and On-
• 1.8 V
±
0.1 V Power Supply
1.8 V
±
0.1 V (SSTL_18) compatible I/O
Die-Termination (ODT) for better signal quality.
• DRAM organizations with 4, 8 and 16 data in/outputs
• Auto-Precharge operation for read and write bursts
• Double Data Rate architecture: two data transfers per
• Auto-Refresh, Self-Refresh and power saving Power-
clock cycle four internal banks for concurrent operation
Down modes
• CAS Latency: 3, 4, 5 and 6
• Average Refresh Period 7.8
µs
at a
T
CASE
lower than
• Burst Length: 4 and 8
85 °C, 3.9
µs
between 85 °C and 95 °C
• Differential clock inputs (CK and CK)
• Programmable self refresh rate via EMRS2 setting
• Programmable partial array refresh via EMRS2 settings
• Bi-directional, differential data strobes (DQS and DQS) are
transmitted / received with data. Edge aligned with read
• DCC enabling via EMRS2 setting
• Full and reduced Strength Data-Output Drivers
data and center-aligned with write data.
• DLL aligns DQ and DQS transitions with clock
• 1kB page size for
×4
&
×8,
2kB page size for
×16
• Packages: P(G)-TFBGA-60 for
×4
&
×8
components,
• DQS can be disabled for single-ended data strobe
operation
P(G)-TFBGA-84 for
×16
components
• RoHS Compliant Products
1)
• Commands entered on each positive clock edge, data and
data mask are referenced to both edges of DQS
• All Speed grades faster than DDR2–400 comply with
DDR2–400 timing specifications when run at a clock rate
• Data masks (DM) for write data
• Posted CAS by programmable additive latency for better
of 200 MHz.
command and data bus efficiency
TABLE 1
Performance Table for –25F and –2.5
Product Type Speed Code
Speed Grade
Max. Clock Frequency
@CL6
@CL5
@CL4
@CL3
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
–25F
DDR2–800D 5–5–5
–2.5
DDR2–800E 6–6–6
400
333
266
200
15
15
45
60
Unit
—
MHz
MHz
MHz
MHz
ns
ns
ns
ns
f
CK6
f
CK5
f
CK4
f
CK3
t
RCD
t
RP
t
RAS
t
RC
400
400
266
200
12.5
12.5
45
57.5
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.12, 2007-05
10062006-YPTZ-CDR7
3
Internet Data Sheet
HY[B/I]18T512[40/80/16]0B2[C/F](L)
512-Mbit Double-Data-Rate-Two SDRAM
TABLE 2
Performance table for –3(S)
Product Type Speed Code
Speed Grade
Max. Clock Frequency
@CL5
@CL4
@CL3
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
–3
DDR2–667C 4–4–4
–3S
DDR2–667D 5–5–5
333
266
200
15
15
45
60
Unit
—
MHz
MHz
MHz
ns
ns
ns
ns
f
CK5
f
CK4
f
CK3
t
RCD
t
RP
t
RAS
t
RC
333
333
200
12
12
45
57
TABLE 3
Performance Table for –3.7
Product Type Speed Code
Speed Grade
Max. Clock Frequency
@CL5
@CL4
@CL3
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
–3.7
DDR2–533C 4–4–4
Unit
—
MHz
MHz
MHz
ns
ns
ns
ns
f
CK5
f
CK4
f
CK3
t
RCD
t
RP
t
RAS
t
RC
266
266
200
15
15
45
60
TABLE 4
Performance Table for –5
Product Type Speed Code
Speed Grade
Max. Clock Frequency
@CL5
@CL4
@CL3
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
–5
DDR2–400B 3–3–3
Units
—
MHz
MHz
MHz
ns
ns
ns
ns
f
CK5
f
CK4
f
CK3
t
RCD
t
RP
t
RAS
t
RC
200
200
200
15
15
40
55
Rev. 1.12, 2007-05
10062006-YPTZ-CDR7
4
Internet Data Sheet
HY[B/I]18T512[40/80/16]0B2[C/F](L)
512-Mbit Double-Data-Rate-Two SDRAM
1.2
Description
Inputs are latched at the cross point of differential clocks (CK
rising and CK falling). All I/Os are synchronized with a single
ended DQS or differential DQS-DQS pair in a source
synchronous fashion.
A 16-bit address bus for
×4
and
×8
organized components
and a 15-bit address bus for
×16
components is used to
convey row, column and bank address information in a RAS-
CAS multiplexing style.
The DDR2 device operates with a 1.8 V
±
0.1 V power
supply. An Auto-Refresh and Self-Refresh mode is provided
along with various power-saving power-down modes.
The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of
operation.
The DDR2 SDRAM is available in PG-TFBGA package.
The 512-Mb DDR2 DRAM is a high-speed Double-Data-
Rate-Two CMOS DRAM device containing 536,870,912 bits
and internally configured as a quad-bank DRAM. The 512-Mb
device is organized as either 32 Mbit
×
4 I/O
×4
banks,
16 Mbit
×8
I/O
×
4 banks or 8 Mbit
×16
I/O
×4
banks chip.
These devices achieve high speed transfer rates starting at
400 Mb/sec/pin for general applications. See
Table 1
for
performance figures.
The device is designed to comply with all DDR2 DRAM key
features:
1. Posted CAS with additive latency,
2. Write latency = read latency - 1,
3. Normal and weak strength data-output driver,
4. Off-Chip Driver (OCD) impedance adjustment
5. On-Die Termination (ODT) function.
All of the control and address inputs are synchronized with a
pair of externally supplied differential clocks.
Rev. 1.12, 2007-05
10062006-YPTZ-CDR7
5
stm32/stm8
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
