December 2006
HYS64T32x00HU–[25F/2.5/3/3S/3.7/5]–B
HYS[64/72]T64x00HU–[25F/2.5/3/3S/3.7/5]–B
HYS[64/72]T128x20HU–[25F/2.5/3/3S/3.7/5]–B
240-Pin unbuffered DDR2 SDRAM Modules
DDR2 SDRAM
UDIMM SDRAM
RoHS Compliant
Internet Data Sheet
Rev. 1.3
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
HYS64T32x00HU–[25F/2.5/3/3S/3.7/5]–B, HYS[64/72]T64x00HU–[25F/2.5/3/3S/3.7/5]–B,
HYS[64/72]T128x20HU–[25F/2.5/3/3S/3.7/5]–B
Revision History: 2006-12, Rev. 1.3
Page
All
4, 5
45, 46
Subjects (major changes since last revision)
Adapted internet edition
Added WhiteBox Products for Speed Grade –3S and –3.7
Added WhiteBox Products for Speed Grade –3S and –3.7 to IDD tables.
70, 74, 78,
Updated SPD codes for –3S and –3.7 WhiteBox Products.
82
Previous Revision: 2006-09, Rev. 1.21
All
43
3
42
24
48
55
Qimonda update
SPD codes updated
Added PC2-6400-555 product types
Added
I
DD
currents
Added Speed Grade bin for DDR2-800D
Added
I
DD
Measurement Contions for DDR2-800D
Added SPD codes for PC2-6400-555 product types
Previous Revision: 2006-06, Rev. 1.2
Previous Revision: 2006-01, Rev. 1.1
Previous Revision: Rev. 1.0
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
techdoc@qimonda.com
qag_techdoc_rev400 / 3.2 QAG / 2006-08-07
03292006-6GMD-RSFT
2
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
1
Overview
This chapter gives an overview of the 240-Pin unbuffered DDR2 SDRAM Modules product family and describes its main
characteristics.
1.1
Features
•
•
•
•
•
•
•
•
•
•
•
Auto Refresh (CBR) and Self Refresh
Programmable self refresh rate via EMRS2 setting
Programmable partial array refresh via EMRS2 settings
Average Refresh Period 7.8
µs
at a
T
CASE
lower than
85 °C, 3.9µs between 85 °C and 95 °C.
DCC enabling via EMRS2 setting
All inputs and outputs SSTL_1.8 compatible
Off-Chip Driver Impedance Adjustment (OCD) and
On-Die Termination (ODT)
Serial Presence Detect with E
2
PROM
UDIMM Dimensions (nominal):
30 mm high, 133.35 mm wide
Based on standard reference layouts Raw Card “C”,
“D”,”E”,”F” and “G“
RoHS compliant products
1)
Feature list and performance tables
• 240-Pin PC2–6400, PC2–5300, PC2–4200 and
PC2–3200 DDR2 SDRAM memory modules.
• 32M
×
64, 64M
×
64, 64M
×
72, 128M
×
64 and 128M
×72
module organization and 32M
×
16, 64M
×
8 chip
organization
• Standard Double-Data-Rate-Two Synchronous DRAMs
(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power
supply
• 256MB, 512MB and 1GB modules built with 512-Mbit
DDR2 SDRAMs in P-TFBGA-84 and P-TFBGA-60
chipsize packages
• All speed grades faster than DDR2–400 comply with
DDR2–400 timing specifications.
• Programmable CAS Latencies (3, 4 and 5),
Burst Length (8 & 4) and Burst Type
TABLE 1
Performance Table
Product Type Speed Code
Speed Grade
Max. Clock Frequency
@CL6
f
CK6
@CL5
f
CK5
@CL4
f
CK4
@CL3
f
CK3
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
–25F
PC2–6400
5–5–5
400
400
266
200
12.5
12.5
45
57.5
–2.5
PC2–6400
6–6–6
400
333
266
200
15
15
45
60
–3
PC2–5300
4–4–4
—
333
333
200
12
12
45
57
–3S
PC2–5300
5–5–5
—
333
266
200
15
15
45
60
–3.7
PC2–4200
4–4–4
—
266
266
200
15
15
45
60
–5
PC2–3200
3–3–3
—
200
200
200
15
15
40
55
Unit
—
MHz
MHz
MHz
MHz
ns
ns
ns
ns
t
RCD
t
RP
t
RAS
t
RC
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
3
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
1.2
Description
The memory array is designed with 512-Mbit Double-Data-
Rate-Two (DDR2) Synchronous DRAMs. Decoupling
capacitors are mounted on the PCB board. The DIMMs
feature serial presence detect based on a serial E
2
PROM
device using the 2-pin I
2
C protocol. The first 128 bytes are
programmed with configuration data and are write protected;
the second 128 bytes are available to the customer.
The Qimonda HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
module family are unbuffered DIMM modules “UDIMMs” with
30 mm height based on DDR2 technology. DIMMs are
available as non-ECC modules in 32M
×
64 (256 MB),
64M
×
64 (512 MB), 128M
×
64(1 GB) and as ECC modules
in 64M
×
72 (512 MB), 128M
×
72(1 GB) organization and
density, intended for mounting into 240-pin connector
sockets.
TABLE 2
Ordering Information for RoHS Compliant Products
Product Type
1)
PC2–6400
HYS64T32000HU–25F–B
HYS64T64000HU–25F–B
HYS72T64000HU–25F–B
HYS64T128020HU–25F–B
HYS72T128020HU–25F–B
PC2–6400
HYS64T32000HU–2.5–B
HYS64T64000HU–2.5–B
HYS72T64000HU–2.5–B
HYS64T128020HU–2.5–B
HYS72T128020HU–2.5–B
PC2–5300
HYS64T32000HU–3–B
HYS64T64000HU–3–B
HYS72T64000HU–3–B
HYS64T128020HU–3–B
HYS72T128020HU–3–B
PC2–5300
HYS64T32000HU–3S–B
HYS64T32900HU–3S–B
HYS64T64000HU–3S–B
HYS64T64900HU–3S–B
HYS72T64000HU–3S–B
HYS64T128020HU–3S–B
HYS64T128920HU–3S–B
HYS72T128020HU–3S–B
256 MB 1R×16 PC2–5300U–555–12–C1
256 MB 1R×16 PC2–5300U–555–12–C1
512 MB 1R×8 PC2–5300U–555–12–D0
512 MB 1R×8 PC2–5300U–555–12–D0
512 MB 1R×8 PC2–5300E–555–12–F0
1 GB 2R×8 PC2–5300U–555–12–E0
1 GB 2R×8 PC2–5300U–555–12–E0
1 GB 2R×8 PC2–5300E–555–12–G0
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, ECC
2 Ranks, Non-ECC
2 Ranks, Non-ECC
2 Ranks, ECC
512 Mbit (×16)
512 Mbit (×16)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
256 MB 1R×16 PC2–5300U–444–12–C1
512 MB 1R×8 PC2–5300U–444–12–D0
512 MB 1R×8 PC2–5300E–444–12–F0
1 GB 2R×8 PC2–5300U–444–12–E0
1 GB 2R×8 PC2–5300E–444–12–G0
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, ECC
2 Ranks, Non-ECC
2 Ranks, ECC
512 Mbit (×16)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
256 MB 1R×16 PC2–6400U–666–12–C1
512 MB 1R×8 PC2–6400U–666–12–D0
512 MB 1R×8 PC2–6400E–666–12–F0
1 GB 2R×8 PC2–6400U–666–12–E0
1 GB 2R×8 PC2–6400E–666–12–G0
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, ECC
2 Ranks, Non-ECC
2 Ranks, ECC
512 Mbit (×16)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
256 MB 1R×16 PC2–6400U–555–12–C1
512 MB 1R×8 PC2–6400U–555–12–D0
512 MB 1R×8 PC2–6400E–555–12–F0
1 GB 2R×8 PC2–6400U–555–12–E0
1 GB 2R×8 PC2–6400E–555–12–G0
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, ECC
2 Ranks, Non-ECC
2 Ranks, ECC
512 Mbit (×16)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
Compliance Code
2)
Description
SDRAM
Technology
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
4
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
Product Type
1)
PC2–4200
HYS64T32000HU–3.7–B
HYS64T32900HU–3.7–B
HYS64T64000HU–3.7–B
HYS64T64900HU–3.7–B
HYS72T64000HU–3.7–B
HYS64T128020HU–3.7–B
HYS64T128920HU–3.7–B
HYS72T128020HU–3.7–B
PC2–3200
HYS64T32000HU–5–B
HYS64T64000HU–5–B
HYS72T64000HU–5–B
HYS64T128020HU–5–B
HYS72T128020HU–5–B
Compliance Code
2)
Description
SDRAM
Technology
512 Mbit (×16)
512 Mbit (×16)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×16)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
256 MB 1R×16 PC2–4200U–444–12–C1
256 MB 1R×16 PC2–4200U–444–12–C1
512 MB 1R×8 PC2–4200U–444–12–D0
512 MB 1R×8 PC2–4200U–444–12–D0
512 MB 1R×8 PC2–4200E–444–12–F0
1 GB 2R×8 PC2–4200U–444–12–E0
1 GB 2R×8 PC2–4200U–444–12–E0
1 GB 2R×8 PC2–4200E–444–12–G0
256 MB 1R×16 PC2–3200U–333–12–C1
512 MB 1R×8 PC2–3200U–333–12–D0
512 MB 1R×8 PC2–3200E–333–12–F0
1 GB 2R×8 PC2–3200U–333–12–E0
1 GB 2R×8 PC2–3200E–333–12–G0
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, ECC
2 Ranks, Non-ECC
2 Ranks, Non-ECC
2 Ranks, ECC
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, ECC
2 Ranks, Non-ECC
2 Ranks, ECC
1) All Product Type numbers end with a place code, designating the silicon die revision. Example: HYS64T64000HU–3.7–B, indicating Rev.
“B” dies are used for DDR2 SDRAM components. For all Qimonda DDR2 module and component nomenclature see
Chapter 6
of this data
sheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200U–444–12–C1”, where
4200U means Unbuffered DIMM modules with 4.26 GB/sec Module Bandwidth and “444-12” means Column Address Strobe (CAS)
latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.2 and
produced on the Raw Card “C”.
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
5
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