January 2007
HYB18T512400AF(L)
HYB18T512800AF(L)
HYB18T512160AF(L)
512-Mbit Double-Data-Rate-Two SDRAM
DDR2 SDRAM
RoHS Compliant Products
Internet Data Sheet
Rev. 1.71
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
HYB18T512400AF(L), HYB18T512800AF(L), HYB18T512160AF(L)
Revision History: 2007-01, Rev. 1.71
Page
All
All
108
57
57
Subjects (major changes since last revision)
Qimonda update
Adapted internet edition
Modified AC Timing Parameters
Changed “Read” to “Write” in condition 4.
Removed text “Maximum power up interval for
V
DD
/
V
DDQ
is specified
As 20.0 ms. The power interval is defined as the amount of time it takes for
V
DD
/
V
DDQ
to power-up From 0 V
to 1.8 V ± 100 mV” from condition 1.
Previous Revision: 2006-05, Rev. 1.7
Previous Revision: 2005-08, Rev. 1.6
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qag_techdoc_rev400 / 3.2 QAG / 2006-08-07
03062006-CPCN-4867
2
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
1
1.1
Overview
Features
• Data masks (DM) for write data
• Posted CAS by programmable additive latency for better
command and data bus efficiency
• Off-Chip-Driver impedance adjustment (OCD) and On-
Die-Termination (ODT) for better signal quality.
• Auto-Precharge operation for read and write bursts
• Auto-Refresh, Self-Refresh and power saving Power-
Down modes
• Average Refresh Period 7.8
µs
at a
T
CASE
lower than
85 °C, 3.9 µs between 85 °C and 95 °C
• High Temperature Self Refresh Mode is supported
• Full and reduced Strength Data-Output Drivers
• 1KByte page size for
×
4 &
×
8, 2 KByte page size for
×
16
• Lead-free Packages: P-TFBGA-60 for
×
4 &
×
8
components, P-TFBGA-84 for
×
16 components
• RoHS Compliant Products
1)
This chapter gives an overview of the 512-Mbit DDR2 SDRAM product family and describes its main characteristics.
The 512-Mbit DDR2 SDRAM offers the following key features:
• 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18)
compatible I/O
• DRAM organisations with 4, 8 and 16 data in/outputs
• Double Data Rate architecture: two data transfers per
clock cycle, four internal banks for concurrent operation
• CAS Latency: 3, 4 and 5
• Burst Length: 4 and 8
• Differential clock inputs (CK and CK)
• Bi-directional, differential data strobes (DQS and DQS) are
transmitted / received with data. Edge aligned with read
data and center-aligned with write data.
• DLL aligns DQ and DQS transitions with clock
• DQS can be disabled for single-ended data strobe
operation
• Commands entered on each positive clock edge, data and
data mask are referenced to both edges of DQS
TABLE 1
Performance table for –3(S)
Product Type Speed Code
Speed Grade
Max. Clock Frequency
@CL5
@CL4
@CL3
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
–3
DDR2–667C 4–4–4
–3S
DDR2–667D 5–5–5
333
266
200
15
15
45
60
Unit
—
MHz
MHz
MHz
ns
ns
ns
ns
f
CK5
f
CK4
f
CK3
t
RCD
t
RP
t
RAS
t
RC
333
333
200
12
12
45
57
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.71, 2007-01
03062006-CPCN-4867
3
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
TABLE 2
Performance table for –3
Product Type Speed Code
Speed Grade
Max. Clock Frequency
@CL5
@CL4
@CL3
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
–3
DDR2–667C 4–4–4
Unit
—
MHz
MHz
MHz
ns
ns
ns
ns
f
CK5
f
CK4
f
CK3
t
RCD
t
RP
t
RAS
t
RC
333
333
200
12
12
45
57
TABLE 3
Performance table for –3S
Product Type Speed Code
Speed Grade
Max. Clock Frequency
@CL5
@CL4
@CL3
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
–3S
DDR2–667D 5–5–5
Unit
—
MHz
MHz
MHz
ns
ns
ns
ns
f
CK5
f
CK4
f
CK3
t
RCD
t
RP
t
RAS
t
RC
333
266
200
15
15
45
60
TABLE 4
High Performance for DDR2–400B and DDR2–533C
Product Type Speed Code
Speed Grade
max. Clock Frequency
@CL5
@CL4
@CL3
min. RAS-CAS-Delay
min. Row Precharge Time
min. Row Active Time
min. Row Cycle Time
–3.7
DDR2–533C 4–4–4
–5
DDR2–400B 3–3–3
200
200
200
15
15
40
55
Unit
—
MHz
MHz
MHz
ns
ns
ns
ns
f
CK5
f
CK4
f
CK3
t
RCD
t
RP
t
RAS
t
RC
266
266
200
15
15
45
60
Rev. 1.71, 2007-01
03062006-CPCN-4867
4
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
1.2
Description
4. Off-Chip Driver (OCD) impedance adjustment
5. On-Die Termination (ODT) function.
All of the control and address inputs are synchronized with a
pair of externally supplied differential clocks. Inputs are
latched at the cross point of differential clocks (CK rising and
CK falling). All I/Os are synchronized with a single ended
DQS or differential DQS-DQS pair in a source synchronous
fashion.
A 16-bit address bus for
×
4 and
×
8 organised components
and a 15-bit address bus for
×
16 components is used to
convey row, column and bank address information .
The DDR2 device operates with a 1.8 V ± 0.1 V power
supply. An Auto-Refresh and Self-Refresh mode is provided
along with various power-saving power-down modes.
The DDR2 SDRAM is available in P-TFBGA package.
The 512-Mbit DDR2 DRAM is a high-speed Double-Data-
Rate-Two CMOS Synchronous DRAM device containing
536,870,912 bits and internally configured as a quad-bank
DRAM. The 512-Mbit device is organized as either 32 Mbit
×
4 I/O
×
4 banks, 16 Mbit
×
8 I/O
×
4 banks or 8 Mbit
×
16 I/O
×
4 banks× chip. These synchronous devices achieve high
speed transfer rates starting at 400 Mbit/sec/pin for general
applications. See
Table 1, Table 2
and
Table 3
for
performance figures.
The device is designed to comply with all DDR2 DRAM key
features.
1. Posted CAS with additive latency,
2. Write latency = read latency - 1,
3. Normal and weak strength data-output driver,
Rev. 1.71, 2007-01
03062006-CPCN-4867
5
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