May 2007
H Y B1 8T C 2568 00 BF
H Y B1 8T C 2561 60 BF
256-Mbit Double-Data-Rate-Two SDRAM
DDR2 SDRAM
RoHS Compliant Products
Internet Data Sheet
Rev. 1.3
Internet Data Sheet
HYB18TC256[80/16]0BF
256-Mbit Double-Data-Rate-Two SDRAM
Revision History: Rev. 1.3, 2007-05
All
2
All
Adapted internet edition
Added product type HYB18TC256800BF
Qimonda template update
Previous Revision: Rev. 1.21, 2007-02
Previous Revision: Rev. 1.2, 2006-07
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qag_techdoc_rev400 / 3.2 QAG / 2006-08-01
07182006-DD60-22E6
2
Internet Data Sheet
HYB18TC256[80/16]0BF
256-Mbit Double-Data-Rate-Two SDRAM
1
Overview
This chapter gives an overview of the 256-Mbit Double-Data-Rate-Two SDRAM product family and describes its main
characteristics.
1.1
Features
The 256-Mbit Double-Data-Rate-Two SDRAM offers the following key features:
• Off-Chip-Driver impedance adjustment (OCD) and On-
• 1.8 V
±
0.1 V Power Supply
• 1.8 V
±
0.1 V (SSTL_18) compatible I/O
Die-Termination (ODT) for better signal quality
• DRAM organizations with 8 and 16 data in/outputs
• Auto-Precharge operation for read and write bursts
• Double Data Rate architecture: two data transfers per
• Auto-Refresh, Self-Refresh and power saving Power-
clock cycle four internal banks for concurrent operation
Down modes
• Programmable CAS Latency: 3, 4, 5 and 6
• Average Refresh Period 7.8
µs
at a
T
CASE
lower than
• Programmable Burst Length: 4 and 8
85 °C, 3.9
µs
between 85 °C and 95 °C
• Differential clock inputs (CK and CK)
• Programmable self refresh rate via EMRS2 setting
• Programmable partial array refresh via EMRS2 settings
• Bi-directional, differential data strobes (DQS and DQS) are
transmitted / received with data. Edge aligned with read
• DCC enabling via EMRS2 setting
• Full and reduced Strength Data-Output Drivers
data and center-aligned with write data.
• DLL aligns DQ and DQS transitions with clock
• 1K page size
• Packages: PG-TFBGA-84, PG-TFBGA-60
• DQS can be disabled for single-ended data strobe
operation
• RoHS Compliant Products
1)
• Commands entered on each positive clock edge, data and
• All Speed grades faster than DDR400 comply with
data mask are referenced to both edges of DQS
DDR400 timing specifications when run at a clock rate of
• Data masks (DM) for write data
200 MHz
• Posted CAS by programmable additive latency for better
command and data bus efficiency
TABLE 1
Performance tables for –2.5
Product Type Speed Code
Speed Grade
Max. Clock Frequency
@CL6
@CL5
@CL4
@CL3
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
–2.5
DDR2–800E 6–6–6
Unit
—
MHz
MHz
MHz
MHz
ns
ns
ns
ns
f
CK6
f
CK5
f
CK4
f
CK3
t
RCD
t
RP
t
RAS
t
RC
400
333
266
200
15
15
45
60
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.3, 2007-05
07182006-DD60-22E6
3
Internet Data Sheet
HYB18TC256[80/16]0BF
256-Mbit Double-Data-Rate-Two SDRAM
TABLE 2
Performance table for –3(S)
Product Type Speed Code
Speed Grade
Max. Clock Frequency
@CL5
@CL4
@CL3
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
–3
DDR2–667C 4–4–4
–3S
DDR2–667D 5–5–5
333
266
200
15
15
45
60
Unit
—
MHz
MHz
MHz
ns
ns
ns
ns
f
CK5
f
CK4
f
CK3
t
RCD
t
RP
t
RAS
t
RC
333
333
200
12
12
45
57
TABLE 3
Performance table for –3.7
Product Type Speed Code
Speed Grade
Max. Clock Frequency
@CL5
@CL4
@CL3
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
–3.7
DDR2–533C 4–4–4
Unit
—
MHz
MHz
MHz
ns
ns
ns
ns
f
CK5
f
CK4
f
CK3
t
RCD
t
RP
t
RAS
t
RC
266
266
200
15
15
45
60
TABLE 4
Performance table for –5
Product Type Speed Code
Speed Grade
Max. Clock Frequency
@CL5
@CL4
@CL3
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
–5
DDR2–400B 3–3–3
Units
—
MHz
MHz
MHz
ns
ns
ns
ns
f
CK5
f
CK4
f
CK3
t
RCD
t
RP
t
RAS
t
RC
200
200
200
15
15
40
55
Rev. 1.3, 2007-05
07182006-DD60-22E6
4
Internet Data Sheet
HYB18TC256[80/16]0BF
256-Mbit Double-Data-Rate-Two SDRAM
1.2
Description
All of the control and address inputs are synchronized with a
pair of externally supplied differential clocks. Inputs are
latched at the cross point of differential clocks (CK rising and
CK falling). All I/Os are synchronized with a single ended
DQS or differential DQS-DQS pair in a source synchronous
fashion.
A 15 bit address bus is used to convey row, column and bank
address information in a RAS-CAS multiplexing style.
The DDR2 device operates with a 1.8 V
±
0.1 V power
supply. An Auto-Refresh and Self-Refresh mode is provided
along with various power-saving power-down modes.
The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of
operation.
The DDR2 SDRAM is available in PG-TFBGA package.
The 256-Mb DDR2 DRAM is a high-speed Double-Data-
Rate-Two CMOS DRAM device containing 536,870,912 bits
and internally configured as a quad -bank DRAM. The 256-
Mb device is organized as either 8 Mbit
×8
I/O
×4
banks or 4
Mbit
×16
I/O
×4
banks chip. These devices achieve high
speed transfer rates starting at 400 Mb/sec/pin for general
applications. See
Table 1
to
Table 4
for performance figures.
The device is designed to comply with all DDR2 DRAM key
features:
1. Posted CAS with additive latency
2. Write latency = read latency - 1
3. Normal and weak strength data-output driver
4. Off-Chip Driver (OCD) impedance adjustment
5. On-Die Termination (ODT) function
TABLE 5
Ordering Information for Lead-Free Products (RoHS Compliant)
Product Type
1)
HYB18TC256800BF-2.5
HYB18TC256160BF-2.5
HYB18TC256800BF-3
HYB18TC256160BF-3
HYB18TC256800BF-3S
HYB18TC256160BF-3S
HYB18TC256800BF-3.7
HYB18TC256160BF-3.7
HYB18TC256800BF-5
HYB18TC256160BF-5
Org.
×8
×16
×8
×16
×8
×16
×8
×16
×8
×16
3-3-3
200
DDR2-400B
4-4-4
266
DDR2-533C
5-5-5
333
DDR2-667D
4-4-4
333
DDR2-667C
CAS-RCD-RP
Latencies
2)3)4)
6-6-6
Clock
(MHz)
400
Speed
DDR2-800E
Package
PG-TFBGA-60
PG-TFBGA-84
PG-TFBGA-60
PG-TFBGA-84
PG-TFBGA-60
PG-TFBGA-84
PG-TFBGA-60
PG-TFBGA-84
PG-TFBGA-60
PG-TFBGA-84
Note
5)
1) Please check with your Qimonda representative that leadtime and availability of your preferred device type and version meet your project
requirements.
2) CAS: Column Address Strobe
3) RCD: Row Column Delay
4) RP: Row Precharge
5) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Note: For product nomenclature see
Chapter 9
of this data sheet
Rev. 1.3, 2007-05
07182006-DD60-22E6
5
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