Internet Data Sheet
HYB18TC1G[80/16]0BF
1-Gbit Double-Data-Rate-Two SDRAM
HYB18TC1G800BF, HYB18TC1G160BF
Revision History: 2007-07, Rev. 1.21
Page
All
14
136
Subjects (major changes since last revision)
Adapted internet edition
Corrected Table 9: Added Ball B2 and B8
Corrected package outline
Editorial changes
Previous Revision: 2007-03, Rev. 1.1
Previous Revision: 2007-03, Rev. 1.2
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02282007-F8UP-4HSU
2
Internet Data Sheet
HYB18TC1G[80/16]0BF
1-Gbit Double-Data-Rate-Two SDRAM
1
Overview
This chapter gives an overview of the 1-Gbit Double-Data-Rate-Two SDRAM product family and describes its main
characteristics.
1.1
Features
The 1-Gbit Double-Data-Rate-Two SDRAM offers the following key features:
• Off-Chip-Driver impedance adjustment (OCD) and On-
• 1.8 V
±
0.1 V Power Supply 1.8 V
±
0.1 V (SSTL_18)
compatible I/O
Die-Termination (ODT) for better signal quality.
• DRAM organizations with 8 and 16 data in/outputs
• Auto-Precharge operation for read and write bursts
• Double Data Rate architecture: two data transfers per
• Auto-Refresh, Self-Refresh and power saving Power-
Down modes
clock cycle four internal banks for concurrent operation
• Programmable CAS Latency: 3, 4, 5 and 6
• Average Refresh Period 7.8
µs
at a
T
CASE
lower than
85 °C, 3.9
µs
between 85 °C and 95 °C
• Programmable Burst Length: 4 and 8
• Programmable self refresh rate via EMRS2 setting
• Differential clock inputs (CK and CK)
• Programmable partial array refresh via EMRS2 settings
• Bi-directional, differential data strobes (DQS and DQS) are
transmitted / received with data. Edge aligned with read
• DCC enabling via EMRS2 setting
• Full and reduced Strength Data-Output Drivers
data and center-aligned with write data.
• DLL aligns DQ and DQS transitions with clock
• 1K page size for
×8,
2K page size for
×16
• Packages: PG-TFBGA-68 for
×8
components, PG-
• DQS can be disabled for single-ended data strobe
operation
TFBGA-84 for
×16
components
• RoHS Compliant Products
1)
• Commands entered on each positive clock edge, data and
data mask are referenced to both edges of DQS
• All Speed grades faster than DDR2–400 comply with
DDR2–400 timing specifications when run at a clock rate
• Data masks (DM) for write data
• Posted CAS by programmable additive latency for better
of 200 MHz.
command and data bus efficiency
A list of the performance tables for the various speeds can be found below
•
Table 1 “Performance tables for –2.5” on Page 4
•
Table 2 “Performance table for –3S” on Page 4
•
Table 3 “Performance table for –3.7” on Page 4
•
Table 4 “Performance Table for –5” on Page 5
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.21, 2007-07
02282007-F8UP-4HSU
3
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