Internet Data Sheet
HY[B/I]25D512[40/80/16]0C[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
Revision History: Rev. 1.41, 2007-12
Adapted internet edition
Added IDD values
Previous Revision: Rev. 1.40, 2007-12
Added HYI25D512800CE-5 and HYI25D512800CF-5,Added HYI25D512800CT-6, HYI25D512800CE-6,
HYI25D512800CT-5,HYI25D512800CC-6, HYI25D512800CF-6 and HYI25D512800CC-5
Package Outline Figures updated
Previous Revision: Rev. 1.31, 2006-09
Qimonda update
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
techdoc@qimonda.com
qag_techdoc_rev411 / 3.31 QAG / 2007-01-22
03292006-3TFJ-HNV3
2
Date: 2007-12-13
Internet Data Sheet
HY[B/I]25D512[40/80/16]0C[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
1
Overview
This chapter gives an overview of the 512-Mbit Double-Data-Rate SDRAM product family and describes its main
characteristics.
1.1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Features
Double data rate architecture: two data transfers per clock cycle
Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver
DQS is edge-aligned with data for reads and is center-aligned with data for writes
Differential clock inputs (CK and CK)
Four internal banks for concurrent operation
Data mask (DM) for write data
DLL aligns DQ and DQS transitions with CK transitions
Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
Programmable CAS latency: 2, 2.5, 3
Programmable burst lengths: 2, 4, or 8
Auto Precharge option for each burst access
Auto Refresh and Self Refresh Modes
RAS-lockout supported
t
RAP
=
t
RCD
7.8
μs
Maximum Average Periodic Refresh Interval
2.5 V (SSTL_2 compatible) I/O
V
DD
= 2.5 V
±
0.2 V
V
DDQ
= 2.5 V
±
0.2 V
Packages: PG-TSOPII-66, PG-TFBGA-60, P-TSOPII-66, P-TFBGA-60
RoHS Compliant Products
TABLE 1
Performance
Part Number Speed Code
Speed Grade
Max. Clock Frequency
Component
@CL3
@CL2.5
@CL2
–5
DDR400B
–6
DDR333B
166
166
133
Unit
—
MHz
MHz
MHz
f
CK3
f
CK2.5
f
CK2
200
166
133
Rev. 1.41, 2007-12
03292006-3TFJ-HNV3
3
Date: 2007-12-13
Internet Data Sheet
HY[B/I]25D512[40/80/16]0C[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
1.2
Description
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write
command. The address bits registered coincident with the
Active command are used to select the bank and row to be
accessed. The address bits registered coincident with the
Read or Write command are used to select the bank and the
starting column location for the burst access.
The DDR SDRAM provides for programmable Read or Write
burst lengths of 2, 4 or 8 locations. An Auto Precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst access. As
with standard SDRAMs, the pipelined, multibank architecture
of DDR SDRAMs allows for concurrent operation, thereby
providing high effective bandwidth by hiding row precharge
and activation time.
An auto refresh mode is provided along with a power-saving
power-down mode. All inputs are compatible with the Industry
Standard for SSTL_2. All outputs are SSTL_2, Class II
compatible.
Note: The functionality described and the timing
specifications included in this data sheet are for the
DLL Enabled mode of operation.
The 512-Mbit is a high-speed CMOS, dynamic random-
access memory containing 536, 870, 912 bits. It is internally
configured as a quad-bank DRAM.
The 512-Mbit Double-Data-Rate SDRAM uses a double-
data-rate architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n prefetch
architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write
access for the 512-Mbit Double-Data-Rate SDRAM
effectively consists of a single 2n-bit wide, one clock cycle
data transfer at the internal DRAM core and two
corresponding n-bit wide, one-half-clock-cycle data transfers
at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver. DQS
is a strobe transmitted by the DDR SDRAM during Reads and
by the memory controller during Writes. DQS is edge-aligned
with data for Reads and center-aligned with data for Writes.
The 512-Mbit Double-Data-Rate SDRAM operates from a
differential clock (CK and CK; the crossing of CK going HIGH
and CK going LOW is referred to as the positive edge of CK).
Commands (address and control signals) are registered at
every positive edge of CK. Input data is registered on both
edges of DQS, and output data is referenced to both edges of
DQS, as well as to both edges of CK.
Rev. 1.41, 2007-12
03292006-3TFJ-HNV3
4
Date: 2007-12-13
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
