March 2007
HYB25D256[40/80/16]0CE(L)
HYB25D256[40/80/16]0C[T/C/F]
HYI25D256[80/16]0C[C/E/F/T]
256-Mbit Double-Data-Rate SDRAM
DDR SDRAM
RoHS Compliant or Lead-Containing
Internet Data Sheet
Rev. 2.3
Internet Data Sheet
HY[B/I]25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
HYB25D256[40/80/16]0CE(L), HYB25D256[40/80/16]0C[T/C/F], HYI25D256[80/16]0C[C/E/F/T]
Revision History: 2007-03, Rev. 2.3
Page
All
17
72
85, 86
Subjects (major changes since last revision)
Adapted internet edition
Corrected table 7 mode register definition
Changed the 1.1 mA to 1.5 mA for low power
Changed the ball size from 0.460 mm to 0.450 mm
Previous Revision: 2007-01, Rev. 2.2
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qag_techdoc_rev400 / 3.2 QAG / 2006-08-07
03062006-8CCM-VPUW
2
Internet Data Sheet
HY[B/I]25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
1
1.1
Overview
Features
•
•
•
•
•
•
•
•
•
•
•
Auto Precharge option for each burst access
Auto Refresh and Self Refresh Modes
RAS-lockout supported
t
RAP
=
t
RCD
7.8
µs
Maximum Average Periodic Refresh Interval
2.5 V (SSTL_2 compatible) I/O
V
DDQ
= 2.5 V
±
0.2 V (DDR200, DDR266, DDR333);
V
DDQ
= 2.6 V
±
0.1 V (DDR400)
V
DD
= 2.5 V
±
0.2 V (DDR200, DDR266, DDR333);
V
DD
= 2.6 V
±
0.1 V (DDR400)
Standard Temperature Range (0
°C
- +70
°C)
or Industrial
Temperature Range (–40
°C
- +85
°C)
P-TFBGA-60-12 package with 3 depopulated rows
(8
×
12 mm
2
)
P-TSOPII-66 package
RoHS
1)
compliant product types available (green product)
This chapter lists all main features of the product family HY[B/I]25D256[16/40/80]0C[E/C/F/T](L) and the ordering information.
• Double data rate architecture: two data transfers per clock
cycle
• Bidirectional data strobe (DQS) is transmitted and
received with data, to be used in capturing data at the
receiver
• DQS is edge-aligned with data for reads and is center-
aligned with data for writes
• Differential clock inputs (CK and CK)
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and
data mask referenced to both edges of DQS
• Burst Lengths: 2, 4, or 8
• CAS Latency: 1.5 (DDR200 only), 2, 2.5, 3
TABLE 1
Performance of –5, –6 and –7
Product Type Speed Code
Speed Grade
Max. Clock
Frequency
Component
@CL3
@CL2.5
@CL2
–5
DDR400B
–6
DDR333B
166
166
133
–7
DDR266A
—
143
133
Unit
—
MHz
MHz
MHz
f
CK3
f
CK2.5
f
CK2
200
166
133
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 2.3, 2007-03
03062006-8CCM-VPUW
3
Internet Data Sheet
HY[B/I]25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
1.2
Description
DQS, as well as to both edges of CK. Read and write
accesses to the DDR SDRAM are burst oriented; accesses
start at a selected location and continue for a programmed
number of locations in a programmed sequence. Accesses
begin with the registration of an Active command, which is
then followed by a Read or Write command. The address bits
registered coincident with the Active command are used to
select the bank and row to be accessed. The address bits
registered coincident with the Read or Write command are
used to select the bank and the starting column location for
the burst access.
The DDR SDRAM provides for programmable Read or Write
burst lengths of 2, 4 or 8 locations. An Auto Precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst access. As
with standard SDRAMs, the pipelined, multibank architecture
of DDR SDRAMs allows for concurrent operation, thereby
providing high effective bandwidth by hiding row precharge
and activation time.
An auto refresh mode is provided along with a power-saving
power-down mode. All inputs are compatible with SSTL_2. All
outputs are SSTL_2, Class II compatible.
Note: The functionality described and the timing
specifications included in this data sheet are for the
DLL Enabled mode of operation.
The 256 Mbit Double-Data-Rate SDRAM is a high-speed
CMOS, dynamic random-access memory containing
268,435,456 bits. It is internally configured as a quad-bank
DRAM.
The 256 Mbit Double-Data-Rate SDRAM uses a double-
data-rate architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n-prefetch
architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write
access
for
the
256 Mbit Double-Data-Rate SDRAM
effectively consists of a single 2n-bit wide, one clock cycle
data transfer at the internal DRAM core and two
corresponding n-bit wide, one-half-clock-cycle data transfers
at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver. DQS
is a strobe transmitted by the DDR SDRAM during Reads and
by the memory controller during Writes. DQS is edge-aligned
with data for Reads and center-aligned with data for Writes.
The 256 Mbit Double-Data-Rate SDRAM operates from a
differential clock (CK and CK; the crossing of CK going HIGH
and CK going LOW is referred to as the positive edge of CK).
Commands (address and control signals) are registered at
every positive edge of CK. Input data is registered on both
edges of DQS, and output data is referenced to both edges of
Rev. 2.3, 2007-03
03062006-8CCM-VPUW
4
Internet Data Sheet
HY[B/I]25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
TABLE 2
Ordering Information for Lead-Free Products (RoHS Compliant)
Product Type
1)
Organization CAS-RCD-RP
Latencies
2.5-3-3
3-3-3
2.5-3-3
Clock (MHz) Speed
Package
Note
Standard Temperature Range (0
°C
- +70
°C)
HYB25D256800CE–5A
×8
HYB25D256160CE–5A
×16
HYB25D256800CE–5
HYB25D256160CE–5
HYB25D256800CE–6
HYB25D256160CE–6
HYB25D256400CE–7
HYB25D256400CF–5
HYB25D256800CF–5
HYB25D256160CF–5
HYB25D256400CF–6
HYB25D256800CF–6
HYB25D256160CF–6
HYI25D256800CE–5
HYI25D256160CE–5
HYI25D256800CE–6
HYI25D256160CE–6
HYI25D256800CF–5
HYI25D256160CF–5
HYI25D256800CF–6
HYI25D256160CF–6
×8
×16
×8
×16
×4
×4
×8
×16
×4
×8
×16
×8
×16
×8
×16
×8
×16
×8
×16
2.5-3-3
166
DDR333
3-3-3
200
DDR400A PG-TFBGA-60
2.5-3-3
166
DDR333
3-3-3
200
DDR400B PG-TSOPII-66
2.5-3-3
166
DDR333
3-3-3
143
200
DDR266A
DDR400A PG-TFBGA-60
166
DDR333
200
DDR400B
200
DDR400A PG-TSOPII-66
HYB25D256800CEL–6
×8
HYB25D256160CEL–6
×16
Industrial Temperature Range (–40
°C
- +85 °C)
Rev. 2.3, 2007-03
03062006-8CCM-VPUW
5
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