June 2007
HY[B/I]39S512400A[E/T]
HY[B/I]39S512800A[E/T]
HY[B/I]39S512160A[E/T]
512-Mbit Synchronous DRAM
SDRAM
RoHS Compliant Products
Internet Data Sheet
Rev. 1.52
Internet Data Sheet
HY[I/B]39S512[40/80/16]0A[E/T]
512-Mbit Synchronous DRAM
HY[B/I]39S512400A[E/T], HY[B/I]39S512800A[E/T], HY[B/I]39S512160A[E/T]
Revision History: 2007-06, Rev. 1.52
Page
All
13
13
15
19
21
Subjects (major changes since last revision)
Adapted internet edition
Corrected operation command "Power Down / Clock suspend ...” in truth table
Corrected operation command "Power Down Exit" to X (WE#)
Corrected text to "After the mode register is set a NOP command is required" , chapter 3.3
Corrected text to "One clock delay is required for mode entry and exit", chapter 3.5
Corrected the line "Input Capacitances: CK" in table 10, chapter 4
Qimonda template
Previous Revision: 2007-05, Rev. 1.5
All
Added more product types
Previous Revision: 2006-01, Rev. 1.4
Previous Revision: 2007-06, Rev. 1.51
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03292006-6Y91-0T2Z
2
Internet Data Sheet
HY[I/B]39S512[40/80/16]0A[E/T]
512-Mbit Synchronous DRAM
1
1.1
•
•
•
•
•
•
•
•
•
•
Overview
Features
•
•
•
•
•
•
•
•
•
Data Mask for Byte Control (x16)
Auto Refresh (CBR) and Self Refresh
Power Down and Clock Suspend Mode
8192 refresh cycles / 64 ms (7.8
µs)
Random Column Address every CLK (1-N Rule)
Single 3.3 V ± 0.3 V Power Supply
LVTTL Interface
Plastic Package : P(G)-TSOPII-54
RoHS compliant product
This chapter lists all main features of the product family HY[I/B]39S512[40/80/16]0A[E/T] and the ordering information.
Fully Synchronous to Positive Clock Edge
0 to 70
°C
Operating Temperature for HYB...
-40 to 85
°C
Operating Temperature for HYI...
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2 & 3
Programmable Wrap Sequence: Sequential or Interleave
Programmable Burst Length: 1, 2, 4, 8 and full page
Multiple Burst Read with Single Write Operation
Automatic and Controlled Precharge Command
Data Mask for Read / Write control (x4, x8, x16)
TABLE 1
Performance
Product Type Speed Code
Speed Grade
Max. Clock Frequency
@CL3
–7.5
PC133–333
1)
Unit
—
MHz
ns
ns
ns
ns
@CL2
1) Max. Frequency CL/
t
RCD /
t
RP
f
CK3
t
CK3
t
AC3
t
CK2
t
AC2
133
7.5
5.4
10
6
Rev. 1.52, 2007-06
03292006-6Y91-0T2Z
3
Internet Data Sheet
HY[I/B]39S512[40/80/16]0A[E/T]
512-Mbit Synchronous DRAM
1.2
Description
The HY[I/B]39S512[40/80/16]0A[E/T] are four bank Synchronous DRAM’s organized as
4 banks
×
32MBit
×
4, 4
banks
×
16MBit
×
8 and 4 banks
×
8Mbit
×
16 respectively
. These synchronous devices achieve high speed data transfer
rates for CAS latencies by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to
a system clock. The chip is fabricated with Qimonda advanced 0.14
µm
512-MBit DRAM process technology.
The device is designed to comply with all industry standards set for synchronous DRAM products, both electrically and
mechanically. All of the control, address, data input and output circuits are synchronized with the positive edge of an externally
supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is
possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and
speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single 3.3 V ± 0.3 V power supply.
All 512-Mbit components are available in P(G)-TSOPII-54 packages.
TABLE 2
Ordering Information for RoHS Compliant Products
Product Type
HYB39S512400AT-7.5
HYB39S512800AT-7.5
HYB39S512160AT-7.5
HYB39S512400AE-7.5
HYB39S512800AE-7.5
HYB39S512160AE-7.5
Industrial Operating Temperature (–40 °C - +85 °C)
HYI39S512400AT-7.5
HYI39S512800AT-7.5
HYI39S512160AT-7.5
HYI39S512400AE-7.5
HYI39S512800AE-7.5
HYI39S512160AE-7.5
PC133-333-520
133MHz 4B
×
32M
×
4 SDRAM
133MHz 4B
×
16M
×
8 SDRAM
133MHz 4B
×
8M
×
16 SDRAM
133MHz 4B
×
32M
×
4 SDRAM
133MHz 4B
×
16M
×
8 SDRAM
133MHz 4B
×
8M
×
16 SDRAM
PG-TSOPII-54
1)
Speed Grade
PC133-333-520
Description
133MHz 4B
×
32M
×
4 SDRAM
133MHz 4B
×
16M
×
8 SDRAM
133MHz 4B
×
8M
×
16 SDRAM
133MHz 4B
×
32M
×
4 SDRAM
133MHz 4B
×
16M
×
8 SDRAM
133MHz 4B
×
8M
×
16 SDRAM
Package
P-TSOPII-54
Note
Standard Operating Temperature (0 °C - +70 °C)
PG-TSOPII-54
1)
P-TSOPII-54
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.52, 2007-06
03292006-6Y91-0T2Z
4
Internet Data Sheet
HY[I/B]39S512[40/80/16]0A[E/T]
512-Mbit Synchronous DRAM
2
2.1
Configuration
Pin Configuration
This chapter contains the pin configuration table and the TSOP package drawing.
Listed below are the pin configurations sections for the various signals of the SDRAM.
TABLE 3
Ball Configuration of the SDRAM
Ball No.
Name
Pin
Type
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Buffer
Type
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Address Signal 9:0, Address Signal 10/Auto precharge
Chip Select
Bank Address Signals 1:0
Function
Clock Signals x4/ x8/ x16 Organization
38
37
18
17
16
19
20
21
23
24
25
26
29
30
31
32
33
34
22
35
36
CLK
CKE
RAS
CAS
WE
CS
BA0
BA1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
Clock Signal CLK
Clock Enable
Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE)
Control Signals x4/ x8/ x16 Organization
Address Signals x4/ x8/ x16 Organization
Rev. 1.52, 2007-06
03292006-6Y91-0T2Z
5
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