October 2007
HYB39S128400F[E/T](L)
HY[B/I]39S128800F[E/T](L)
HY[B/I]39S128160F[E/T](L)
H Y B 39 S 128 407F E
128-MBit Synchronous DRAM
Green Product
SDRAM
Data Sheet
Rev. 1.32
Data Sheet
HY[B/I]39S128[40/80/16][0/7]F[E/T](L)
128-MBit Synchronous DRAM
HYB39S128400F[E/T](L), HY[B/I]39S128800F[E/T](L), HY[B/I]39S128160F[E/T](L)
Revision History: 2007-10, Rev. 1.32
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Subjects (major changes since last revision)
Adapted Internet Version
Corrected number of refresh cycles
Corrected operation command "Power Down / Clock suspend ...” in truth table
Corrected text to "After the mode register is set a NOP command is required"
Corrected text to "One clock delay is required for mode entry and exit", chapter 3.5
Corrected the line "Input Capacitances: CK" in table 10, chapter 4
Corrected tCK MIN in table 14
Corrected CLE setup time in table 14
Corrected mode register definition
IDD for low power option 0.8 mA
“Transition time” replaced by “Transition Time of Clock (Rise and Fall)”
Added HYI39S128800FT-7, HYI39S128800FE-7, HYI39S128160FT-7, HYI39S128160FE-7 and
HYB39S128407FE-7
Previous Revision: 2007-06, Rev. 1.31
Previous Revision: 2007-03, Rev. 1.30
Previous Revision: 2006-10, Rev. 1.20
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Your feedback will help us to continuously improve the quality of this document.
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qag_techdoc_rev400 / 3.2 QAG / 2006-08-01
10122006-I6LJ-WV3H
2
Data Sheet
HY[B/I]39S128[40/80/16][0/7]F[E/T](L)
128-MBit Synchronous DRAM
1
1.1
•
•
•
•
•
•
•
•
•
Overview
Features
•
•
•
•
•
•
•
•
•
Data Mask for Read / Write control (x4, x8)
Data Mask for Byte Control (x16)
Auto Refresh (CBR) and Self Refresh
Power Down and Clock Suspend Mode
4096 refresh cycles / 64 ms (15.6
μs)
Random Column Address every CLK (1-N Rule)
Single 3.3 V ± 0.3 V Power Supply
LVTTL Interface
Plastic Packages: P(G)–TSOPII–54 400 mil width
This chapter lists all main features of the product family HY[B/I]39S128[40/80/16][0/7]F[E/T](L) and the ordering information.
Fully Synchronous to Positive Clock Edge
0 to 70
°C
Standard Operating Temperature
-40 to 85
°C
Industrial Operating Temperature
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2 & 3
Programmable Wrap Sequence: Sequential or Interleave
Programmable Burst Length: 1, 2, 4, 8 and full page
Multiple Burst Read with Single Write Operation
Automatic and Controlled Precharge Command
TABLE 1
Performance
Product Type Speed Code
Speed Grade
Max. Clock Frequency
@CL3
–7
PC133–222
Unit
—
MHz
ns
ns
ns
ns
@CL2
f
CK3
t
CK3
t
AC3
t
CK2
t
AC2
143
7
5.4
7.5
5.4
1.2
Description
The HY[B/I]39S128[40/80/16][0/7]F[E/T](L) are four bank Synchronous DRAM’s organized as 32 MBit x4, 16 MBit x8
and 8 Mbit x16 respectively. These synchronous devices achieve high speed data transfer rates for CAS latencies by
employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip
is fabricated with Qimonda’s advanced 0.11
μm
128-MBit DRAM process technology.
The device is designed to comply with all industry standards set for synchronous DRAM products, both electrically and
mechanically. All of the control, address, data input and output circuits are synchronized with the positive edge of an externally
supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is
possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and
speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single 3.3 V ± 0.3 V power supply.
All 128-Mbit components are available in P(G)–TSOPII–54 packages.
Rev. 1.32, 2007-10
10122006-I6LJ-WV3H
3
Data Sheet
HY[B/I]39S128[40/80/16][0/7]F[E/T](L)
128-MBit Synchronous DRAM
TABLE 2
Ordering Information for Lead-Containing Products
Product Type
HYB39S128400FT-7
HYB39S128400FTL-7
HYB39S128800FT-7
HYB39S128800FTL-7
HYB39S128160FT-7
HYB39S128160FTL-7
Industrial Operating Temperature (-40 to 85
°C)
HYI39S128800FT-7
HYI39S128160FT-7
PC133–222–520
143MHz 16M x 8 SDRAM
143MHz 8M x 16 SDRAM
P-TSOPII-54
143MHz 8M x 16 SDRAM
143MHz 16M x 8 SDRAM
Speed Grade
PC133–222–520
Description
143MHz 32M x 4 SDRAM
Package
P-TSOPII-54
Standard Operating Temperature (0 to 70
°C)
TABLE 3
Ordering Information for RoHS Compliant Products
Product Type
HYB39S128400FE-7
HYB39S128400FEL-7
HYB39S128407FE-7
HYB39S128800FE-7
HYB39S128800FEL-7
HYB39S128160FE-7
HYB39S128160FEL-7
Industrial Operating Temperature (-40 to 85
°C)
HYI39S128800FE-7
HYI39S128160FE-7
PC133–222–520
143MHz 16M x 8 SDRAM
143MHz 8M x 16 SDRAM
PG-TSOPII-54
1)
Speed Grade
PC133–222–520
Description
143MHz 32M x 4 SDRAM
Package
PG-TSOPII-54
Note
1)
Standard Operating Temperature (0 to 70
°C)
143MHz 16M x 8 SDRAM
143MHz 8M x 16 SDRAM
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.32, 2007-10
10122006-I6LJ-WV3H
4
Data Sheet
HY[B/I]39S128[40/80/16][0/7]F[E/T](L)
128-MBit Synchronous DRAM
2
Chip Configuration
This chapter contains the pin configuration table, the TSOP package drawing, and the block diagrams for the
×4, ×8, ×16
organization of the SDRAM.
2.1
Pin Description
TABLE 4
Pin Configuration of the SDRAM
Listed below are the pin configurations sections for the various signals of the SDRAM
Ball No.
Name
Pin
Type
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Buffer
Type
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Function
Clock Signals
×4/×8/×16
Organization
38
37
18
17
16
19
20
21
23
24
25
26
29
30
31
32
33
34
22
35
CLK
CKE
RAS
CAS
WE
CS
BA0
BA1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
Clock Signal CK
Clock Enable
Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE)
Control Signals
×4/×8/×16
Organization
Chip Select
Bank Address Signals 1:0
Address Signal, Address Signal 10/Auto precharge
Address Signals
×4/×8/×16
Organization
Rev. 1.32, 2007-10
10122006-I6LJ-WV3H
5
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