Preliminary
74LVTH16500 Low Voltage 18-Bit Universal Bus Transceivers
May 2000
Revised May 2000
74LVTH16500
Low Voltage 18-Bit Universal Bus Transceivers
with 3-STATE Outputs (Preliminary)
General Description
The LVTH16500 is an 18-bit universal bus transceiver
combining D-type latches and D-type flip-flops to allow
data flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs.
The LVTH16500 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
The transceiver is designed for low voltage (3.3V) V
CC
applications, but with the capability to provide a TTL inter-
face to a 5V environment. The LVTH16500 is fabricated
with an advanced BiCMOS technology to achieve high
speed operation similar to 5V ABT while maintaining low
power dissipation.
Features
s
Input and output interface capability to systems at
5V V
CC
s
Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs
s
Live insertion/extraction permitted
s
Power Up/Down high impedance provides glitch-free
bus loading
s
Outputs source/sink
−32
mA/+64 mA
s
Functionally compatible with the 74 series 16500
s
Latch-up performance exceeds 500 mA
Ordering Code:
Order Number
74LVTH16500MEA
74LVTH16500MTD
Package Number
MS56A
MTD56
Package Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix “X” to the ordering code.
© 2000 Fairchild Semiconductor Corporation
DS012447
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Preliminary
74LVTH16500
Connection Diagram
Pin Descriptions
Pin Names
A
1
–A
18
B
1
–B
18
LEAB, LEBA
OEAB, OEBA
Description
Data Register A Inputs/3-STATE Outputs
Data Register B Inputs/3-STATE Outputs
Latch Enable Inputs
Output Enable Inputs
CLKAB, CLKBA Clock Pulse Inputs
Function Table
(Note 1)
Inputs
OEAB
L
H
H
H
H
H
H
LEAB
X
H
H
L
L
L
L
CLKAB
X
X
X
↓
↓
H
L
A
X
L
H
L
H
X
X
Output
B
Z
L
H
L
H
B
0
(Note 2)
B
0
(Note 3)
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
↓ =
HIGH-to-LOW Clock Transition
Note 1:
A-to-B data flow is shown: B-to-A flow is similar but uses OEBA,
LEBA, and CLKBA.
Note 2:
Output level before the indicated steady-state input conditions
were established.
Note 3:
Output level before the indicated steady-state input conditions
were established, provided that CLKAB was LOW before LEAB went LOW.
Functional Description
For A-to-B data flow, the device operates in the transparent
mode when LEAB is HIGH. When LEAB is LOW, the A
data is latched if CLKAB is held at a HIGH or LOW logic
level. If LEAB is LOW, the A bus data is stored in the latch/
flip-flop on the HIGH-to-LOW transition of CLKAB. Output-
enable OEAB is active-HIGH. When OEAB is HIGH, the
outputs are active. When OEAB is LOW, the outputs are in
the high-impedance state.
Data flow for B-to-A is similar to that of A-to-B but uses
OEBA, LEBA, and CLKBA. The output enables are com-
plementary (OEAB is active-HIGH and OEBA is active-
LOW).
Logic Diagram
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2
Preliminary
74LVTH16500
Absolute Maximum Ratings
(Note 4)
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
Parameter
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
Value
−0.5
to
+4.6
−0.5
to
+7.0
−0.5
to
+7.0
Output in 3-STATE
−0.5
to
+7.0
Output in HIGH or LOW State (Note 5)
−50
−50
64
128
±64
±128
−65
to
+150
V
I
<
GND
V
O
<
GND
V
O
>
V
CC
V
O
>
V
CC
Output at HIGH State
Output at LOW State
Conditions
Units
V
V
V
V
mA
mA
mA
mA
mA
°C
Recommended Operating Conditions
Symbol
V
CC
V
I
I
OH
I
OL
T
A
∆t/∆V
Supply Voltage
Input Voltage
HIGH-Level Output Current
LOW-Level Output Current
Free-Air Operating Temperature
Input Edge Rate, V
IN
=
0.8V – 2.0V, V
CC
=
3.0V
−40
0
Parameter
Min
2.7
0
Max
3.6
5.5
−32
64
85
10
Units
V
V
mA
mA
°C
ns/V
Note 4:
Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 5:
I
O
Absolute Maximum Rating must be observed.
3
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Preliminary
74LVTH16500
DC Electrical Characteristics
Symbol
V
IK
V
IH
V
IL
V
OH
Parameter
Input Clamp Diode Voltage
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
V
CC
(V)
2.7
2.7–3.6
2.7–3.6
2.7–3.6
2.7
3.0
V
OL
Output LOW Voltage
2.7
2.7
3.0
3.0
3.0
I
I(HOLD)
I
I(OD)
I
I
Bushold Input Minimum Drive
Bushold Input Over-Drive
Current to Change State
Input Current
Control Pins
Data Pins
I
OFF
I
PU/PD
I
OZL
I
OZH
I
OZH
+
I
CCH
I
CCL
I
CCZ
I
CCZ
+
∆I
CC
Power Off Leakage Current
Power Up/Down 3-STATE
Output Current
3-STATE Output Leakage Current
3-STATE Output Leakage Current
3-STATE Output Leakage Current
Power Supply Current
Power Supply Current
Power Supply Current
Power Supply Current
Increase in Power Supply Current
(Note 8)
Note 6:
An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 7:
An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 8:
This is the increase in supply current for each input that is at the specified voltage level rather than V
CC
or GND.
T
A
= −40°C
to
+85°C
Min
2.0
0.8
V
CC
−
0.2
2.4
2.0
0.2
0.5
0.4
0.5
0.55
75
−75
500
−500
10
±1
−5
1
±100
±100
−5
5
10
0.19
5
0.19
0.19
0.2
Max
−1.2
Units
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
mA
mA
mA
mA
mA
Conditions
I
I
= −18
mA
V
O
≤
0.1V or
V
O
≥
V
CC
−
0.1V
I
OH
= −100 µA
I
OH
= −8
mA
I
OH
= −32
mA
I
OL
=
100
µA
I
OL
=
24 mA
I
OL
=
16 mA
I
OL
=
32 mA
I
OL
=
64 mA
V
I
=
0.8V
V
I
=
2.0V
(Note 6)
(Note 7)
V
I
=
5.5V
V
I
=
0V or V
CC
V
I
=
0V
V
I
=
V
CC
0V
≤
V
I
or V
O
≤
5.5V
V
O
=
0.5V to 3.0V
V
I
=
GND or V
CC
V
O
=
0.0V
V
O
=
3.6V
V
CC
<
V
O
≤
5.5V
Outputs HIGH
Outputs LOW
Outputs Disabled
V
CC
≤
V
O
≤
5.5V,
Outputs Disabled
One Input at V
CC
−
0.6V
Other Inputs at V
CC
or GND
3.0
3.0
3.6
3.6
3.6
0
0–1.5V
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
Dynamic Switching Characteristics
Symbol
V
OLP
V
OLV
Parameter
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
V
CC
(V)
3.3
3.3
Min
(Note 9)
T
A
=
25°C
Typ
0.8
−0.8
Max
Conditions
Units
V
V
C
L
=
50 pF, R
L
=
500Ω
(Note 10)
(Note 10)
Note 9:
Characterized in SSOP package. Guaranteed parameter, but not tested.
Note 10:
Max number of outputs defined as (n). n−1 data inputs are driven 0V to 3V. Output under test held LOW.
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4
Preliminary
74LVTH16500
AC Electrical Characteristics
T
A
= −40°C
to
+85°C,
C
L
=
50 pF, R
L
=
500
Ω
Symbol
Parameter
V
CC
=
3.3
±
0.3V
Min
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
Setup Time
A before CLKAB
B before CLKBA
A or B before LE, CLK HIGH
A or B before LE, CLK LOW
t
H
t
W
Hold Time
Pulse Duration
A or B after CLK
A or B after LE
LE HIGH
CLK HIGH or LOW
t
OSLH
t
OSHL
Output to Output Skew (Note 11)
Output Disable Time
Propagation Delay
Data to Outputs
Propagation Delay
LEBA or LEAB to B or A
Propagation Delay
CLKBA or CLKAB to B or A
Output Enable Time
150
1.3
1.3
1.5
1.5
1.3
1.3
1.3
1.3
1.7
1.7
2.9
2.9
1.4
2.9
0.4
1.6
3.3
3.3
1.0
1.0
3.7
3.7
5.1
5.1
5.0
5.0
4.8
4.8
5.8
5.8
Max
V
CC
=
2.7V
Min
150
1.3
1.3
1.5
1.5
1.3
1.3
1.3
1.3
1.7
1.7
2.9
2.9
ns
0.5
2.3
0.4
1.6
3.3
ns
3.3
1.0
1.0
ns
ns
4.0
4.0
5.7
5.7
5.9
5.9
5.5
5.5
6.3
6.3
Max
MHz
ns
ns
ns
ns
ns
Units
Note 11:
Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
).
Capacitance
(Note 12)
Symbol
C
IN
C
I/O
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
V
CC
=
0V, V
I
=
0V or V
CC
V
CC
=
3.0V, V
O
=
0V or V
CC
Typical
4
8
Units
pF
pF
Note 12:
Capacitance is measured at frequency f
=
1 MHz, per MIL-STD-883, Method 3012.
5
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