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IDT6116LA35P

产品描述2K X 8 STANDARD SRAM, 55 ns, CDIP24
产品类别存储   
文件大小111KB,共11页
制造商IDT(艾迪悌)
官网地址http://www.idt.com/
下载文档 详细参数 全文预览

IDT6116LA35P概述

2K X 8 STANDARD SRAM, 55 ns, CDIP24

2K × 8 标准存储器, 55 ns, CDIP24

IDT6116LA35P规格参数

参数名称属性值
功能数量1
端子数量24
最小工作温度-55 Cel
最大工作温度125 Cel
额定供电电压5 V
最小供电/工作电压4.5 V
最大供电/工作电压5.5 V
加工封装描述0.600 INCH, CERAMIC, DIP-24
each_compliYes
状态Active
sub_categorySRAMs
ccess_time_max55 ns
i_o_typeCOMMON
jesd_30_codeR-GDIP-T24
jesd_609_codee0
存储密度16384 bi
内存IC类型STANDARD SRAM
内存宽度8
moisture_sensitivity_levelNOT SPECIFIED
端口数1
位数2048 words
位数2K
操作模式ASYNCHRONOUS
组织2KX8
输出特性3-STATE
输出使能YES
包装材料CERAMIC, GLASS-SEALED
ckage_codeDIP
ckage_equivalence_codeDIP24,.6
包装形状RECTANGULAR
包装尺寸IN-LINE
串行并行PARALLEL
eak_reflow_temperature__cel_225
wer_supplies__v_5
qualification_statusCOMMERCIAL
screening_levelMIL-STD-883 Class B
seated_height_max4.83 mm
standby_current_max0.0100 Am
standby_voltage_mi4.5 V
最大供电电压0.1000 Am
表面贴装NO
工艺CMOS
温度等级MILITARY
端子涂层TIN LEAD
端子形式THROUGH-HOLE
端子间距2.54 mm
端子位置DUAL
ime_peak_reflow_temperature_max__s_20
length32 mm
width15.24 mm

文档预览

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CMOS Static RAM
16K (2K x 8-Bit)
IDT6116SA
IDT6116LA
x
Features
High-speed access and chip select times
– Military: 20/25/35/45/55/70/90/120/150ns (max.)
– Industrial: 20/25/35/45ns (max.)
– Commercial: 15/20/25/35/45ns (max.)
Low-power consumption
Battery backup operation
– 2V data retention voltage (LA version only)
Produced with advanced CMOS high-performance
technology
CMOS process virtually eliminates alpha particle soft-error
rates
Input and output directly TTL-compatible
Static operation: no clocks or refresh required
Available in ceramic and plastic 24-pin DIP, 24-pin Thin Dip,
24-pin SOIC and 24-pin SOJ
Military product compliant to MIL-STD-833, Class B
Description
The IDT6116SA/LA is a 16,384-bit high-speed static RAM
organized as 2K x 8. It is fabricated using IDT's high-performance,
high-reliability CMOS technology.
Access times as fast as 15ns are available. The circuit also offers a
reduced power standby mode. When
CS
goes HIGH, the circuit will
automatically go to, and remain in, a standby power mode, as long
as
CS
remains HIGH. This capability provides significant system level
power and cooling savings. The low-power (LA) version also offers a
battery backup data retention capability where the circuit typically
consumes only 1µW to 4µW operating off a 2V battery.
All inputs and outputs of the IDT6116SA/LA are TTL-compatible. Fully
static asynchronous circuitry is used, requiring no clocks or refreshing
for operation.
The IDT6116SA/LA is packaged in 24-pin 600 and 300 mil plastic or
ceramic DIP, 24-lead gull-wing SOIC, and 24-lead J-bend SOJ providing
high board-level packing densities.
Military grade product is manufactured in compliance to the latest
version of MIL-STD-883, Class B, making it ideally suited to military
temperature applications demanding the highest level of performance and
reliability.
x
x
x
x
x
x
x
x
Functional Block Diagram
A
0
V
CC
ADDRESS
DECODER
A
10
128 X 128
MEMORY
ARRAY
GND
I/O
0
INPUT
DATA
CIRCUIT
I/O
7
I/O CONTROL
,
CS
OE
WE
CONTROL
CIRCUIT
3089 drw 01
FEBRUARY 2001
1
©2000 Integrated Device Technology, Inc.
DSC-3089/03

 
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