Lower Power
3.3V CMOS Fast SRAM
256K (32K x 8-Bit)
Features
Ideal for high-performance processor secondary cache
Commercial (0°C to +70°C) and Industrial (–40°C to +85°C)
temperature range options
Fast access times:
– Commercial and Industrial: 10/12/15/20ns
Low standby current (maximum):
– 2mA full standby
Small packages for space-efficient layouts:
– 28-pin 300 mil SOJ
– 28-pin TSOP Type I
Produced with advanced high-performance CMOS
technology
Inputs and outputs are LVTTL-compatible
Single 3.3V(±0.3V) power supply
IDT71V256SA
◆
◆
◆
◆
◆
Description
The IDT71V256SA is a 262,144-bit high-speed static RAM organized
as 32K x 8. It is fabricated using IDT’s high-performance, high-reliability
CMOS technology.
The IDT71V256SA has outstanding low power characteristics while
at the same time maintaining very high performance. Address access
times of as fast as 10ns are ideal for 3.3V secondary cache in 3.3V
desktop designs.
When power management logic puts the IDT71V256SA in standby
mode, its very low power characteristics contribute to extended battery life.
By taking
CS
HIGH, the SRAM will automatically go to a low power standby
mode and will remain in standby as long as
CS
remains HIGH. Further-
more, under full standby mode (CS at CMOS level, f=0), power consump-
tion is guaranteed to always be less than 6.6mW and typically will be much
smaller.
The IDT71V256SA is packaged in a 28-pin 300 mil SOJ and a 28-pin
300 mil TSOP Type I.
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Functional Block Diagram
A
0
ADDRESS
DECODER
A
14
262,144 BIT
MEMORY ARRAY
V
CC
GND
I/O
0
INPUT
DATA
CIRCUIT
I/O
7
I/O CONTROL
CS
OE
WE
,
CONTROL
CIRCUIT
3101 drw 01
JANUARY 2004
1
©2004 Integrated Device Technology, Inc.
DSC-3101/08
IDT71V256SA
3.3V CMOS Static RAM 256K (32K x 8-Bit)
Commercial and Industrial Temperature Ranges
Pin Configurations
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
Truth Table
(1)
WE
V
CC
WE
A
13
A
8
A
9
A
11
OE
A
10
CS
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
3101 drw 02
CS
H
V
HC
L
L
L
OE
X
X
H
L
X
I/O
High-Z
High-Z
High-Z
D
OUT
D
IN
Function
Standby (I
SB
)
Standby (I
SB1
)
Output Disable
Read
Write
3101 tbl 02
X
X
H
H
L
SO28-5
22
21
20
19
18
17
16
15
NOTE:
1. H = V
IH
, L = V
IL
, X = Don’t Care
,
DIP/SOJ
Top View
OE
A
11
A
9
A
8
A
13
WE
V
CC
A
14
A
12
A
7
A
6
A
5
A
4
A
3
22
23
24
25
26
27
28
1
2
3
4
5
6
7
Absolute Maximum Ratings
(1)
Symbol
V
CC
Rating
Supply Voltage
Relative to GND
Terminal Voltage
Relative to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Com'l.
-0.5 to +4.6
-0.5 to V
CC
+0.5
-55 to +125
-55 to +125
1.0
50
Unit
V
V
o
21
20
19
18
17
16
15
14
13
12
11
10
9
8
SO28-8
A
10
CS
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
0
A
1
A
2
V
TERM
(2)
T
BIAS
T
STG
P
T
C
C
o
W
mA
3101 tbl 03
,
I
OUT
TSOP
Top View
Pin Descriptions
Name
A
0
- A
14
I/O
0
- I/O
7
CS
WE
OE
GND
V
CC
3101 drw 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. Input, Output, and I/O terminals; 4.6V maximum.
Description
Addresses
Data Input/Output
Chip Select
Write Enable
Output Enable
Ground
Power
3101 tbl 01
Capacitance
Symbol
C
IN
C
OUT
(T
A
= +25°C, f = 1.0MHz, SOJ package)
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
6
7
Unit
pF
pF
3101 tbl 04
NOTE:
1. This parameter is determined by device characterization, but is not production
tested.
Recommended Operating
Temperature and Supply Voltage
Grade
Commercial
Industrial
Temperature
0
O
C to +70
O
C
-40
O
C to +85
O
C
GND
0V
0V
Vcc
3.3V ± 0.3V
3.3V ± 0.3V
3101 tbl 05
2
IDT71V256SA
3.3V CMOS Static RAM 256K (32K x 8-Bit)
Commercial and Industrial Temperature Ranges
Recommended DC Operating
Conditions
Symbol
V
CC
GND
V
IH
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage - Inputs
Input High Voltage - I/O
Input Low Voltage
Min.
3.0
0
2.0
2.0
-0.3
(1)
Typ.
3.3
0
____
____
Max.
3.6
0
5.0
V
CC
+0.3
0.8
Unit
V
V
V
V
V
3101 tbl 06
____
NOTE:
1. V
IL
(min.) = –2.0V for pulse width less than 5ns, once per cycle.
DC Electrical Characteristics
(1)
Symbol
I
CC
I
SB
I
SB1
Parameter
Dynamic Operating Current
CS
< V
IL
, Outputs
Open, V
CC
= Max., f = f
MAX
(2)
Standby Power Supply Current (TTL Level)
CS
= V
IH
, V
CC
= Max., Outputs Open, f = f
MAX
(2)
Full Standby Power Supply Current (CMOS Level)
CS
> V
HC
, V
CC
= Max., Outputs Open, f = 0
(2)
,
V
IN
< V
LC
or V
IN
> V
HC
(V
CC
= 3.3V ± 0.3V, V
LC
= 0.2V, V
HC
= V
CC
- 0.2V, Commercial and Industrial Temperture Ranges)
71V256SA10
100
20
2
71V256SA12
90
20
2
71V256SA15
85
20
2
71V256SA20
85
20
2
Unit
mA
mA
mA
NOTES:
1. All values are maximum guaranteed values.
2. f
MAX
= 1/t
RC
, only address inputs cycling at f
MAX
; f = 0 means that no inputs are cycling.
3101 tbl 07
DC Electrical Characteristics
(V
CC
= 3.3V± 0.3V)
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
IDT71V256SA
Parameter
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Conditions
V
CC
= Max., V
IN =
GND to V
CC
V
CC
= Max.,
CS
= V
IH
, V
OUT
= GND to V
CC
I
OL
= 8mA, V
CC
= Min.
I
OH
= -4mA, V
CC
= Min.
Min.
___
Typ.
___
Max.
2
2
0.4
___
Unit
µA
µA
V
V
3101 tbl 08
___
___
___
___
___
2.4
6.42
3
IDT71V256SA
3.3V CMOS Static RAM 256K (32K x 8-Bit)
Commercial and Industrial Temperature Ranges
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
3ns
1.5V
1.5V
See Figures 1 and 2
3101 tbl 09
3.3V
320Ω
DATA
OUT
350Ω
30pF*
DATA
OUT
3.3V
320Ω
,
350Ω
5pF*
,
3101 drw 05
3101 drw 04
Figure 1. AC Test Load
*Includes scope and jig capacitances
Figure 2. AC Test Load
(for t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
OW
, t
WHZ
)
AC Electrical Characteristics
(V
CC
= 3.3V ± 0.3V, Commercial and Industrial Temperature Ranges)
71V256SA10
Symbol
Parameter
Min.
Max.
71V256SA12
Min.
Max.
71V256SA15
Min.
Max.
71V256SA20
Min.
Max.
Unit
Read Cycle
t
RC
t
AA
t
ACS
t
CLZ
(1)
t
CHZ
(1)
t
OE
t
OLZ
(1)
t
OHZ
(1)
t
OH
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select to Output in Low-Z
Chip Select to Output in High-Z
Output Enable to Output Valid
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
Output Hold from Address Change
10
____
____
____
12
____
____
____
15
____
____
____
20
____
____
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
____
12
12
____
15
15
____
20
20
____
5
0
____
5
0
____
5
0
____
5
0
____
8
6
____
8
6
____
9
7
____
10
8
____
3
2
3
3
2
3
0
0
3
0
0
3
6
____
6
____
7
____
8
____
Write Cycle
t
WC
t
AW
t
CW
t
AS
t
WP
t
WR
t
DW
t
DH
t
OW
(1)
t
WHZ
(1)
Write Cycle Time
Address Valid to End-of-Write
Chip Select to End-of-Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End-of-Write
Write Enable to Output in High-Z
10
9
9
0
9
0
6
0
4
1
____
____
____
____
____
12
9
9
0
9
0
6
0
4
1
____
____
____
____
____
15
10
10
0
10
0
7
0
4
1
____
____
____
____
____
20
15
15
0
15
0
8
0
4
1
____
____
____
____
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3101 tbl 10
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
8
8
9
10
NOTE:
1. This parameter guaranteed with the AC test load (Figure 2) by device characterization, but is not production tested.
4
IDT71V256SA
3.3V CMOS Static RAM 256K (32K x 8-Bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 1
(1)
t
RC
ADDRESS
t
AA
OE
t
OE
t
OLZ
CS
t
ACS
t
CLZ (2)
DATA
OUT
DATA VALID
3101 drw 06
t
OH
(2)
t
OHZ
(2)
t
CHZ
(2)
,
NOTES:
1.
WE
is HIGH for Read cycle.
2. Transition is measured ±200mV from steady state.
Timing Waveform of Read Cycle No. 2
(1,2,4)
t
RC
ADDRESS
t
AA
t
OH
DATA
OUT
PREVIOUS DATA VALID
DATA VALID
3101 drw 07
t
OH
,
Timing Waveform of Read Cycle No. 3
(1,3,4)
CS
t
ACS
t
CLZ (5)
DATA
OUT
NOTES:
1.
WE
is HIGH for Read cycle.
2. Device is continuously selected,
CS
is LOW.
3. Address valid prior to or coincident with
CS
transition LOW.
4.
OE
is LOW.
5. Transition is measured ±200mV from steady state.
t
CHZ
DATA VALID
(5)
3101 drw 08
,
6.42
5
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