IS41C16256C
IS41LV16256C
256Kx16
4Mb DRAM WITH EDO PAGE MODE
FEATURES
• TTL compatible inputs and outputs; tri-state I/O
• Refresh Interval: 512 cycles/8 ms
• Refresh Mode : RAS-Only, CAS-before-RAS (CBR),
and Hidden
• JEDEC standard pinout
• Single power supply:
5V ± 10% (IS41C16256C)
3.3V ± 10% (IS41LV16256C)
• Byte Write and Byte Read operation via two CAS
• Industrial Temperature Range -40°C to +85°C
JANUARY 2013
DESCRIPTION
The IS41C16256C and IS41LV16256C are 262,144 x 16-bit
high-performance CMOS Dynamic Random Access Memo-
ries. Both products offer accelerated cycle access EDO
Page Mode. EDO Page Mode allows 512 random accesses
within a single row with access cycle time as short as 14ns
per 16-bit word. It is asynchronous, as it does not require a
clock signal input to synchronize commands and I/O.
These features make the IS41C/LV16256C ideally suited for
high band-width graphics, digital signal processing, high-
performance computing systems, and peripheral applications
that run without a clock to synchronize with the DRAM.
The IS41C/LV16256C is packaged in 40-pin TSOP
(Type II).
KEY TIMING PARAMETERS
Parameter
Max. RAS Access Time (t
rac
)
Max. CAS Access Time (t
cac
)
Max. Column Address Access Time (t
aa
)
Min. EDO Page Mode Cycle Time (t
pc
)
Min. Read/Write Cycle Time (t
rc
)
-35
35
13
18
14
60
Unit
ns
ns
ns
ns
ns
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex-
pected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon
Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.
Rev. A
1/31/2013
1
IS41C16256C
IS41LV16256C
Functional Description
The IS41C/LV16256C is a CMOS DRAM optimized for
high-speed bandwidth, low power applications. During
READ or WRITE cycles, each bit is uniquely addressed
through the 18 address bits. These are entered nine
bits (A0-A8) at a time. The row address is latched by
the Row Address Strobe (RAS). The column address
is latched by the Column Address Strobe (CAS).
RAS
is used to latch the first nine bits and
CAS
is used the
latter nine bits.
The IS41C/LV16256C has two CAS controls,
LCAS
and
UCAS. The LCAS
and
UCAS
inputs internally gener-
ates a
CAS
signal functioning in an identical manner to
the single
CAS input on the other 256K x 16 DRAMs.
The key difference is that each CAS controls its corre-
sponding I/O tristate logic (in conjunction with OE and
WE
and
RAS). LCAS controls I/O0 through I/O7 and
UCAS controls I/O8 through I/O15.
The IS41C/LV16256C CAS function is determined by
the first
CAS
(LCAS or
UCAS) transitioning LOW and
the last transitioning back HIGH. The two CAS controls
give the IS41C/LV16256C both BYTE READ and BYTE
WRITE cycle capabilities.
Refresh Cycle
To retain data, 512 refresh cycles are required in each
8 ms period. There are two ways to refresh the memo-
ry.
1. By clocking each of the 512 row addresses (A0
through A8) with RAS at least once every 8 ms. Any
read, write, read-modify-write or
RAS-only
cycle re-
freshes the addressed row.
2. Using a
CAS-before-RAS
refresh cycle.
CAS-before-
RAS
refresh is activated by the falling edge of
RAS,
while holding
CAS LOW. In CAS-before-RAS
refresh
cycle, an internal 9-bit counter provides the row ad-
dresses and the external address inputs are ignored.
CAS-before-RAS
is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Extended Data Out Page Mode
Memory Cycle
A memory cycle is initiated by bring
RAS LOW and it
is terminated by returning both
RAS
and
CAS
HIGH.
To ensures proper device operation and data integrity
any memory cycle, once initiated, must not be ended
or aborted before the minimum t
ras
time has expired.
A new cycle must not be initiated until the minimum
precharge time t
rp
, t
cp
has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of
CAS
or
OE,
whichever occurs last, while holding
WE
HIGH.
The column address must be held for a minimum time
specified by t
ar
. Data Out becomes valid only when
t
rac
, t
aa
, t
cac
and t
oea
are all satisfied. As a result, the
access time is dependent on the timing relationships
between these parameters.
EDO page mode operation permits all 512 columns
within a selected row to be randomly accessed at a
high data rate.
In EDO page mode read cycle, the data-out is held to
the next
CAS
cycle’s falling edge, instead of the ris-
ing edge. For this reason, the valid data output time
in EDO page mode is extended compared with the
fast page mode. In the fast page mode, the valid data
output time becomes shorter as the
CAS
cycle time
becomes shorter. Therefore, in EDO page mode, the
timing margin in read cycle is larger than that of the
fast page mode even if the
CAS
cycle time becomes
shorter.
In EDO page mode, due to the extended data function,
the
CAS
cycle time can be shorter than in the fast page
mode if the timing margin is the same.
The EDO page mode allows both read and write opera-
tions during one
RAS
cycle, but the performance is
equivalent to that of the fast page mode in that case.
Power-On
Write Cycle
A write cycle is initiated by the falling edge of
CAS
and
WE, whichever occurs last. The input data must be
valid at or before the falling edge of
CAS
or
WE,
which-
ever occurs last.
During Power-on, RAS,
CAS, UCAS, LCAS,
and
WE
must all track with V
dd
(HIGH) to avoid current surges,
and allow initialization to continue. An inital pause of
200 µs is required followed by a minimum of eight ini-
tialization cycles (any combination of cycles containing
a
RAS
signal).
Integrated Silicon Solution, Inc.
Rev.
A
1/31/2013
5
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