MC74LVX8053
Analog Multiplexer/
Demultiplexer
High−Performance Silicon−Gate CMOS
The MC74LVX8053 utilizes silicon−gate CMOS technology to
achieve fast propagation delays, low ON resistances, and low OFF
leakage currents. This analog multiplexer/demultiplexer controls
analog voltages that may vary across the complete power supply range
(from V
CC
to GND).
The LVX8053 is similar in pinout to the high−speed HC4053A, and
the metal−gate MC14053B. The Channel−Select inputs determine
which one of the Analog Inputs/Outputs is to be connected, by means
of an analog switch, to the Common Output/Input. When the Enable
pin is HIGH, all analog switches are turned off.
The Channel−Select and Enable inputs are compatible with standard
CMOS outputs; with pull−up resistors they are compatible with
LSTTL outputs.
This device has been designed so that the ON resistance (R
on
) is
more linear over input voltage than R
on
of metal−gate CMOS analog
switches.
Features
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SOIC−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F
PIN ASSIGNMENT
V
CC
16
Y
15
X
14
X1
13
X0
12
A
11
B
10
C
9
1
Y1
2
Y0
3
Z1
4
Z
5
6
7
8
GND
•
•
•
•
•
•
•
•
•
•
Fast Switching and Propagation Speeds
Low Crosstalk Between Switches
Diode Protection on All Inputs/Outputs
Analog Power Supply Range (V
CC
− GND) = 2.5 to 6.0 V
Digital (Control) Power Supply Range (V
CC
− GND) = 2.5 to 6.0 V
Improved Linearity and Lower ON Resistance Than Metal−Gate
Counterparts
Low Noise
In Compliance With the Requirements of JEDEC Standard No. 7A
Chip Complexity: LVX8053 − 156 FETs or 39 Equivalent Gates
These Devices are Pb−Free and are RoHS Compliant
Z0 Enable NC
MARKING DIAGRAMS
16
LVX8053G
AWLYWW
1
SOIC−16
16
LVX
8053
ALYWG
G
1
TSSOP−16
LVX8053
A
WL, L
Y
WW, W
G or
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
©
Semiconductor Components Industries, LLC, 2014
1
August, 2014 − Rev. 6
Publication Order Number:
MC74LVX8053/D
MC74LVX8053
X0
13
X1
Y0
1
Y1
Z0
3
Z1
A
10
CHANNEL‐SELECT
B
INPUTS
9
C
6
ENABLE
11
5
2
12
14
FUNCTION TABLE − MC74LVX8053
X
Control Inputs
Select
B
A
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
X
X SWITCH
ANALOG
INPUTS/OUTPUTS
Y SWITCH
15
Y
COMMON
OUTPUTS/INPUTS
Enable
L
L
L
L
L
L
L
L
H
X = Don’t Care
C
L
L
L
L
H
H
H
H
X
ON Channels
Z0
Z0
Z0
Z0
Z1
Z1
Z1
Z1
Y0
Y0
Y1
Y1
Y0
Y0
Y1
Y1
NONE
X0
X1
X0
X1
X0
X1
X0
X1
Z SWITCH
4
Z
PIN 16 = V
CC
PIN 8 = GND
NOTE: This device allows independent control of each switch.
Channel−Select Input A controls the X−Switch, Input B controls the
Y−Switch and Input C controls the Z−Switch
LOGIC DIAGRAM
Triple Single−Pole, Double−Position Plus Common Off
MAXIMUM RATINGS
Symbol
V
CC
V
IS
V
in
I
P
D
T
stg
T
L
Parameter
Positive DC Supply Voltage
Analog Input Voltage
Digital Input Voltage (Referenced to GND)
DC Current, Into or Out of Any Pin
Power Dissipation in Still Air,
Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
SOIC Package†
TSSOP Package†
(Referenced to GND)
Value
–0.5 to +7.0
−0.5 to V
CC
+ 0.5
–0.5 to V
CC
+ 0.5
±20
500
450
–65 to +150
260
Unit
V
V
V
mA
mW
_C
_C
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND
v
(V
in
or V
out
)
v
V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating: SOIC Package: –7 mW/_C from 65_ to 125_C
TSSOP Package: −6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IS
V
in
V
IO
*
T
A
t
r
, t
f
Positive DC Supply Voltage
Analog Input Voltage
Digital Input Voltage (Referenced to GND)
Static or Dynamic Voltage Across Switch
Operating Temperature Range, All Package Types
Input Rise/Fall Time (Channel Select or Enable Inputs)
V
CC
= 3.3 V
±
0.3 V
V
CC
= 5.0 V
±
0.5 V
0
0
100
20
– 55
Parameter
(Referenced to GND)
Min
2.5
0.0
GND
Max
6.0
V
CC
V
CC
1.2
+ 85
Unit
V
V
V
V
_C
ns/V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
*For voltage drops across switch greater than 1.2 V (switch on), excessive V
CC
current may be drawn; i.e., the current out of the switch may
contain both V
CC
and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
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2
MC74LVX8053
DC CHARACTERISTICS — Digital Section
(Voltages Referenced to GND)
V
CC
V
2.5
3.0
4.5
5.5
2.5
3.0
4.5
5.5
5.5
5.5
Guaranteed Limit
−55 to 25°C
1.50
2.10
3.15
3.85
0.5
0.9
1.35
1.65
±0.1
4
≤
85°C
1.50
2.10
3.15
3.85
0.5
0.9
1.35
1.65
±1.0
40
≤
125°C
1.50
2.10
3.15
3.85
0.5
0.9
1.35
1.65
±1.0
160
Unit
V
Symbol
V
IH
Parameter
Minimum High−Level Input Voltage,
Channel−Select or Enable Inputs
Condition
R
on
= Per Spec
V
IL
Maximum Low−Level Input Voltage,
Channel−Select or Enable Inputs
R
on
= Per Spec
V
I
in
I
CC
Maximum Input Leakage Current,
Channel−Select or Enable Inputs
Maximum Quiescent Supply
Current (per Package)
V
in
= V
CC
or GND,
Channel Select, Enable and
V
IS
= V
CC
or GND; V
IO
= 0 V
mA
mA
DC ELECTRICAL CHARACTERISTICS
Analog Section
V
CC
V
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
5.5
Guaranteed Limit
−55 to 25°C
40
30
25
30
25
20
15
8.0
8.0
0.1
v
85_C
45
32
28
35
28
25
20
12
12
0.5
≤
125°C
50
37
30
40
35
30
25
15
15
1.0
W
Unit
W
Symbol
R
on
Parameter
Maximum “ON” Resistance
Test Conditions
V
in
= V
IL
or V
IH
V
IS
= V
CC
to GND
|I
S
|
v
10.0 mA (Figures 1, 2)
V
in
= V
IL
or V
IH
V
IS
= V
CC
or GND (Endpoints)
|I
S
|
v
10.0 mA (Figures 1, 2)
DR
on
Maximum Difference in “ON”
Resistance Between Any Two
Channels in the Same Package
Maximum Off−Channel Leakage
Current, Any One Channel
Maximum Off−Channel
Leakage Current,
Common Channel
V
in
= V
IL
or V
IH
V
IS
= 1/2 (V
CC
− GND)
|I
S
|
v
10.0 mA
V
in
= V
IL
or V
IH
;
V
IO
= V
CC
or GND;
Switch Off (Figure 3)
V
in
= V
IL
or V
IH
;
V
IO
= V
CC
or GND;
Switch Off (Figure 4)
V
in
= V
IL
or V
IH
;
Switch−to−Switch = V
CC
or
GND; (Figure 5)
I
off
mA
5.5
0.1
1.0
2.0
I
on
Maximum On−Channel
Leakage Current,
Channel−to−Channel
5.5
0.1
1.0
2.0
mA
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3
MC74LVX8053
AC CHARACTERISTICS
(C
L
= 50 pF, Input t
r
= t
f
= 3 ns)
Symbol
t
PLH
,
t
PHL
Parameter
Maximum Propagation Delay, Channel−Select to Analog Output
(Figure 9)
V
CC
V
2.5
3.0
4.5
5.5
2.5
3.0
4.5
5.5
2.5
3.0
4.5
5.5
2.5
3.0
4.5
5.5
Analog I/O
Common O/I
Feedthrough
Guaranteed Limit
−55 to 25°C
30
20
15
15
4.0
3.0
1.0
1.0
30
20
15
15
20
12
8.0
8.0
10
35
50
1.0
≤
85°C
35
25
18
18
6.0
5.0
2.0
2.0
35
25
18
18
25
14
10
10
10
35
50
1.0
≤
125°C
40
30
22
20
8.0
6.0
2.0
2.0
40
30
22
20
30
15
12
12
10
35
50
1.0
Unit
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Analog Input to Analog Output
(Figure 10)
ns
t
PLZ
,
t
PHZ
Maximum Propagation Delay, Enable to Analog Output
(Figure 11)
ns
t
PZL
,
t
PZH
Maximum Propagation Delay, Enable to Analog Output
(Figure 11)
ns
C
in
C
I/O
Maximum Input Capacitance, Channel−Select or Enable Inputs
Maximum Capacitance
(All Switches Off)
pF
pF
Typical @ 25°C, V
CC
= 5.0 V
C
PD
Power Dissipation Capacitance (Figure 13)*
* Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC2
f + I
CC
V
CC
.
45
pF
ADDITIONAL APPLICATION CHARACTERISTICS
(GND = 0 V)
V
CC
V
Limit*
25°C
120
120
120
−50
−50
−50
−37
−37
−37
25
105
135
35
145
190
−50
−50
−50
−60
−60
−60
%
3.0
4.5
5.5
0.10
0.08
0.05
dB
mV
PP
dB
Unit
MHz
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
Symbol
BW
Parameter
Maximum On−Channel Bandwidth
or Minimum Frequency Response
(Figure 6)
Condition
f
in
= 1MHz Sine Wave; Adjust f
in
Voltage to Obtain
0dBm at V
OS
; Increase f
in
Frequency Until dB
Meter Reads −3dB;
R
L
= 50W, C
L
= 10pF
f
in
= Sine Wave; Adjust f
in
Voltage to Obtain 0dBm
at V
IS
f
in
= 10kHz, R
L
= 600W, C
L
= 50pF
−
Off−Channel Feedthrough Isolation
(Figure 7)
f
in
= 1.0MHz, R
L
= 50W, C
L
= 10pF
−
Feedthrough Noise.
Channel−Select Input to Common
I/O (Figure 8)
V
in
≤
1MHz Square Wave (t
r
= t
f
= 6ns); Adjust R
L
at Setup so that I
S
= 0A;
Enable = GND
R
L
= 600W, C
L
= 50pF
R
L
= 10kW, C
L
= 10pF
−
Crosstalk Between Any Two
Switches (Figure 12)
f
in
= Sine Wave; Adjust f
in
Voltage to Obtain 0dBm
at V
IS
f
in
= 10kHz, R
L
= 600W, C
L
= 50pF
f
in
= 1.0MHz, R
L
= 50W, C
L
= 10pF
THD
Total Harmonic Distortion
(Figure 14)
f
in
= 1kHz, R
L
= 10kW, C
L
= 50pF
THD = THD
measured
− THD
source
V
IS
= 2.0V
PP
sine wave
V
IS
= 4.0V
PP
sine wave
V
IS
= 5.5V
PP
sine wave
*Limits not tested. Determined by design and verified by qualification.
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MC74LVX8053
45
40
Ron , ON RESISTANCE (OHMS)
35
30
25
20
15
10
5
00
1.0
2.0
V
IN
, INPUT VOLTAGE (VOLTS)
3.0
4.0
125°C
85°C
25°C
- 55°C
Figure 1a. Typical On Resistance, V
CC
= 3.0 V
30
Ron , ON RESISTANCE (OHMS)
125°C
85°C
25°C
- 55°C
Ron , ON RESISTANCE (OHMS)
25
20
15
10
5
0
30
25
20
15
10
5
0
1.0
2.0
3.0
4.0
5.0
0
125°C
85°C
25°C
- 55°C
0
1.0
2.0
3.0
4.0
5.0
6.0
V
IN
, INPUT VOLTAGE (VOLTS)
V
IN
, INPUT VOLTAGE (VOLTS)
Figure 1b. Typical On Resistance, V
CC
= 4.5 V
Figure 1c. Typical On Resistance, V
CC
= 5.5 V
PLOTTER
PROGRAMMABLE
POWER
SUPPLY
-
+
MINI COMPUTER
DC ANALYZER
V
CC
DEVICE
UNDER TEST
ANALOG IN
COMMON OUT
GND
GND
Figure 2. On Resistance Test Set−Up
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