Freescale Semiconductor
Addendum
Document Number: QFN_Addendum
Rev. 0, 07/2014
Addendum for New QFN
Package Migration
This addendum provides the changes to the 98A case outline numbers for products covered in this book.
Case outlines were changed because of the migration from gold wire to copper wire in some packages. See
the table below for the old (gold wire) package versus the new (copper wire) package.
To view the new drawing, go to Freescale.com and search on the new 98A package number for your
device.
For more information about QFN package use, see EB806:
Electrical Connection Recommendations for
the Exposed Pad on QFN and DFN Packages.
© Freescale Semiconductor, Inc., 2014. All rights reserved.
Part Number
MC68HC908JW32
MC9S08AC16
MC9S908AC60
MC9S08AC128
MC9S08AW60
MC9S08GB60A
MC9S08GT16A
MC9S08JM16
MC9S08JM60
MC9S08LL16
MC9S08QE128
MC9S08QE32
MC9S08RG60
MCF51CN128
MC9RS08LA8
MC9S08GT16A
MC9S908QE32
MC9S908QE8
MC9S08JS16
MC9S08QB8
MC9S08QG8
MC9S08SH8
MC9RS08KB12
MC9S08QG8
MC9RS08KB12
MC9S08QG8
MC9RS08KA2
6 DFN
Package Description
48 QFN
Original (gold wire)
Current (copper wire)
package document number package document number
98ARH99048A
98ASA00466D
48 QFN
32 QFN
32 QFN
32 QFN
24 QFN
98ARL10606D
98ARH99035A
98ARE10566D
98ASA00071D
98ARL10608D
98ASA00466D
98ASA00473D
98ASA00473D
98ASA00736D
98ASA00734D
24 QFN
24 QFN
24 QFN
16 QFN
8 DFN
98ARL10605D
98ARE10714D
98ASA00087D
98ARE10614D
98ARL10557D
98ASA00474D
98ASA00474D
98ASA00602D
98ASA00671D
98ASA00672D
98ARL10602D
98ASA00735D
Addendum for New QFN Package Migration, Rev. 0
2
Freescale Semiconductor
Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MC9S08JS16
Rev. 4, 4/2009
MC9S08JS16
MC9S08JS16 Series
Covers:
MC9S08JS16
MC9S08JS8
MC9S08JS16L
MC9S08JS8L
Features:
• 8-Bit HCS08 Central Processor Unit (CPU)
– 48 MHz HCS08 CPU (central processor unit)
– 24 MHz internal bus frequency
– Support for up to 32 interrupt/reset sources
• Memory Options
– Up to 16 KB of on-chip in-circuit programmable flash
memory with block protection and security options
– Up to 512 bytes of on-chip RAM
– 256 bytes of USB RAM
• Clock Source Options
– Clock source options include crystal, resonator, external
clock
– MCG (multi-purpose clock generator) — PLL and FLL;
internal reference clock with trim adjustment
• System Protection
– Optional computer operating properly (COP) reset with
option to run from independent 1 kHz internal clock
source or the bus clock
– Low-voltage detection
– Illegal opcode detection with reset
– Illegal address detection with reset
• Power-Saving Modes
– Wait plus two stops
• USB Bootload
– Mass erase entire flash array
– Partial erase flash array — erase all flash blocks except
for the first 1 KB of flash
– Program flash
• Peripherals
–
USB —
USB 2.0 full-speed (12 Mbps) with dedicated
on-chip 3.3 V regulator and transceiver; supports
endpoint 0 and up to 6 additional endpoints
TBD
20 W-SOIC
Case 751D
24 QFN
Case 1982-01
–
SPI
— One 8- or 16-bit selectable serial peripheral
interface module with a receive data buffer hardware
match function
–
SCI
— One serial communications interface module
with optional 13 bit break. Full duplex non-return to zero
(NRZ); LIN master extended break generation; LIN
slave extended break detection; wakeup on active edge
–
MTIM
— One 8-bit modulo counter with 8-bit prescaler
and overflow interrupt
–
TPM
— One 2-channel 16-bit timer/pulse-width
modulator (TPM) module; selectable input capture,
output compare, and edge-aligned PWM capability on
each channel; timer module may be configured for
buffered, centered PWM (CPWM) on all channels
–
KBI
— 8-pin keyboard interrupt module
–
RTC
— Real-time counter with binary- or
decimal-based prescaler
–
CRC
— Hardware CRC generator circuit using 16-bit
shift register; CRC16-CCITT compliancy with
x
16
+x
12
+x
5
+1 polynomial
• Input/Output
– Software selectable pullups on ports when used as inputs
– Software selectable slew rate control on ports when used
as outputs
– Software selectable drive strength on ports when used as
outputs
– Master reset pin and power-on reset (POR)
– Internal pullup on RESET, IRQ, and BKGD/MS pins to
reduce customer system cost
• Package Options
– 24-pin quad flat no-lead (QFN)
– 20-pin small outline IC package (SOIC)
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2008-2009. All rights reserved.
Table of Contents
1
2
3
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
3.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . .6
3.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . .6
3.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .7
3.4 Electrostatic Discharge (ESD) Protection Characteristics8
3.5 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.6 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .15
3.7 External Oscillator (XOSC) Characteristics . . . . . . . . .17
3.8 MCG Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .18
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . .
3.9.2 Timer/PWM (TPM) Module Timing. . . . . . . . . .
3.10 SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.11 Flash Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12 USB Electricals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Mechanical Drawings. . . . . . . . . . . . . . . . . . . . . . . . . .
3.9
19
19
20
21
24
25
26
26
26
4
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will
be the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document.
Revision
Date
Description of Changes
1
2
3
4
9/1/2008
1/8/2009
3/9/2009
4/24/2009
Initial public released
In
Table 7,
changed the parameter description of RI
DD
and S3I
DD,
the typicals of
RI
DD
were changed as well.
Corrected the 24-pin QFN case number and doc. number information.
Added new parts information about MC9S08JS16L and MC9S08JS8L.
Related Documentation
Find the most current versions of all documents at: http://www.freescale.com
Reference Manual
(MC9S08JS16RM)
Contains extensive product information including modes of operation, memory,
resets and interrupts, register definition, port pins, CPU, and all module
information.
MC9S08JS16 Series MCU Data Sheet, Rev. 4
2
Freescale Semiconductor
MCU Block Diagram
1
MCU Block Diagram
ON-CHIP ICE AND
DEBUG MODULE (DBG)
FULL SPEED
USB
USB ENDPOINT TRANSCEIVER
RAM
USB
MODULE
The block diagram,
Figure 1,
shows the structure of the MC9S08JS16 series MCU.
HCS08 CORE
USBDP
USBDN
BKGD/MS
BDC
CPU
PTA0/KBIP0/TPMCH0
PTA1/KBIP1/MISO
RESET
HCS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
8-BIT KEYBOARD
INTERRUPT MODULE (KBI)
KBIPx 8
PTA2/KBIP2/MOSI
PORT A
MISO
PTA3/KBIP3/SPSCK
PTA4/KBIP4/SS
PTA5/KBIP5/TPMCH1
PTA6/KBIP6/RxD
PTA7/KBIP7/TxD
TPMCH0
IRQ
8-/16-BIT
COP
IRQ
LVD
SERIAL PERIPHERAL
INTERFACE MODULE (SPI)
MOSI
SPSCK
SS
RxD
TxD
USER FLASH (IN BYTES)
MC9S08JS16 = 16,384
MC9S08JS16L = 16,384
MC9S08JS8 = 8,192
MC9S08JS8L = 8,192
USER RAM (IN BYTES)
512
SERIAL COMMUNICATIONS
INTERFACE MODULE (SCI)
2-CHANNEL TIMER/PWM
MODULE (TPM)
TPMCH1
TCLK
PTB0/IRQ/TCLK
PTB1/RESET
PTB2/BKGD/MS
PTB3/BLMS
MODULE (MTIM)
MULTI-PURPOSE CLOCK
GENERATOR (MCG)
V
SSOSC
V
DD
V
SS
LOW-POWER OSCILLATOR
SYSTEM
VOLTAGE
REGULATOR
16-BIT
Cyclic Redundancy
Check Generator
MODULE (CRC)
EXTAL
XTAL
PORT B
Bootloader ROM (IN BYTES)
4096
8-BIT MODULO TIMER
PTB4/XTAL
PTB5/EXTAL
V
USB33
USB 3.3 V VOLTAGE REGULATOR
REAL-TIME COUNTER
(RTC)
NOTES:
1. Port pins are software configurable with pullup device if input port.
2. Pin contains software configurable pullup/pulldown device if IRQ is enabled (IRQPE = 1). Pulldown is enabled if
rising edge detect is selected (IRQEDG = 1).
3. IRQ does not have a clamp diode to V
DD
. IRQ must not be driven above V
DD
.
4. RESET contains integrated pullup device if PTB1 enabled as reset pin function (RSTPE = 1).
5. Pin contains integrated pullup device.
6. When pin functions as KBI (KBIPEn = 1) and associated pin is configured to enable the pullup device, KBEDGn can
be used to reconfigure the pullup as a pulldown device.
Figure 1. MC9S08JS16 Series Block Diagram
MC9S08JS16 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
3
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