Low Skew, ÷2/4,÷4/5/6,
Differential-to-3.3V LVPECL Clock Generator
87339I-11
Data Sheet
G
ENERAL
D
ESCRIPTION
T h e 8 7 3 3 9 I - 1 1 i s a l ow s kew, h i g h p e r fo r m a n c e
Differential-to-3.3V LVPECL Clock Generator/Divider. The
87339I-11 has one differential clock input pair. The CLK,
nCLK pair can accept most standard differential input
levels. The clock enable isinternally synchronized to
eliminate runt pulses on theoutputs during asynchronous as-
sertion/deassertion of the clock enable pin.
Guaranteed output and par t-to-par t skew charac-
teristics make the 87339I-11 ideal for clock distribution
applications demanding well defined performance and
repeatability.
F
EATURES
•
Dual ÷2, ÷4 differential 3.3V LVPECL outputs;
Dual ÷4, ÷5, ÷6 differential 3.3V LVPECL outputs
•
One differential CLK, nCLK input pair
•
CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
•
Maximum clock input frequency: 1GHz
•
Translates any single ended input signal (LVCMOS, LVTTL,
GTL) to LVPECL levels with resistor bias on nCLK input
•
Output skew: 35ps (maximum)
•
Part-to-part skew: 385ps (maximum)
•
Bank skew: Bank A - 20ps (maximum)
Bank B - 20ps (maximum)
•
Propagation delay: 2.1ns (maximum)
•
LVPECL mode operating voltage supply range:
V
CC
= 3V to 3.6V, V
EE
= 0V
•
Available in lead-free (RoHS 6) package
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
87339I-11
20-Lead TSSOP
6.50mm x 4.40mm x 0.92 package body
G Package
Top View
20-Lead SOIC, 300MIL
7.5mm x 12.8mm x 2.25mm package body
M Package
Top View
©2016 Integrated Device Technology, Inc
1
Revision B January 25, 2016
87339I-11 Data Sheet
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 8, 20
2
3
4
5
6
7
Name
V
CC
nCLK_EN
DIV_SELB0
CLK
nCLK
RESERVED
MR
Power
Input
Input
Input
Input
Reserve
Input
Type
Description
Positive supply pins.
Pulldown Clock enable. LVCMOS / LVTTL interface levels. See Table 3.
Selects divide value for Bank B outputs as described in Table 3.
Pulldown
LVCMOS / LVTTL interface levels.
Pulldown Non-inverting differential clock input.
Pullup
Inverting differential clock input.
Reserve pin.
Active High Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx to go
Pulldown
high. When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS / LVTTL interface levels.
Selects divide value for Bank B outputs as described in Table 3.
Pulldown
LVCMOS / LVTTL interface levels.
Selects divide value for Bank A outputs as described in Table 3.
Pulldown
LVCMOS / LVTTL interface levels.
Negative supply pin.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
9
10
11
12, 13
14, 15
16, 17
18, 19
DIV_SELB1
DIV_SELA
V
EE
nQB1, QB1
nQB0, QB0
nQA1, QA1
nQA0, QA0
Input
Input
Power
Output
Output
Output
Output
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
©2016 Integrated Device Technology, Inc
2
Revision B January 25, 2016
87339I-11 Data Sheet
T
ABLE
3. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Inputs
MR
1
0
0
0
0
0
0
0
0
0
nCLK_EN
X
1
0
0
0
0
0
0
0
0
DIV_SELA
X
X
0
0
0
0
1
1
1
1
DIV_SELB0
X
X
0
0
1
1
0
0
1
1
DIV_SELB1
X
X
0
1
0
1
0
1
0
1
QA0, QA1
LOW
HIGH
Outputs
nQA0, nQA1
QB0, QB1
LOW
Not Switch-
ing
÷4
÷5
÷6
÷5
÷4
÷5
÷6
÷5
nQB0, nQB1
HIGH
Not Switching
÷4
÷5
÷6
÷5
÷4
÷5
÷6
÷5
Not Switch-
Not Switching
ing
÷2
÷2
÷2
÷2
÷4
÷4
÷4
÷4
÷2
÷2
÷2
÷2
÷4
÷4
÷4
÷4
NOTE: After nCLK_EN switches, the clock outputs stop switching following a rising and falling input clock edge.
F
IGURE
1A. MR T
IMING
D
IAGRAM
F
IGURE
1B.
N
CLK_EN T
IMING
D
IAGRAM
©2016 Integrated Device Technology, Inc
3
Revision B January 25, 2016
87339I-11 Data Sheet
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
4.6V
-0.5V to V
CC
+ 0.5 V
50mA
100mA
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the
DC Characteristics
or
AC Charac-
teristics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Package Thermal Impedance,
θ
JA
20 Lead TSSOP
73.2°C/W (0 lfpm)
20 Lead SOIC
46.2°C/W (0 lfpm)
Storage Temperature, T
STG
-65°C to 150°C
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 3.3V±0.3V, T
A
= -40°C
TO
85°C
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.0
Typical
3.3
Maximum
3.6
105
Units
V
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= 3.3V±0.3V, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
nCLK_EN, MR,
DIV_SELA, DIV_SELBx
nCLK_EN, MR,
DIV_SELA, DIV_SELBx
V
IN
= V
CC
= 3.6V
V
IN
= 0V, V
CC
= 3.6V
-5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
CC
+ 0.3
0.8
150
Units
V
V
µA
µA
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
CC
= 3.3V±0.3V, T
A
= -40°C
TO
85°C
Symbol
I
IH
I
IL
V
PP
V
CMR
Parameter
Input High Current
Input Low Current
nCLK
CLK
nCLK
CLK
Test Conditions
V
IN
= V
CC
= 3.6V
V
IN
= V
CC
= 3.6V
V
IN
= 0V, V
CC
= 3.6V
V
IN
= 0V, V
CC
= 3.6V
-150
-5
0.15
1.3
V
CC
- 0.85
Minimum
Typical
Maximum
5
150
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
Common Mode Input Voltage;
V
EE
+ 0.5
NOTE 1, 2
NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is V
CC
+ 0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
©2016 Integrated Device Technology, Inc
4
Revision B January 25, 2016
87339I-11 Data Sheet
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
CC
= 3.3V±0.3V, T
A
= -40°C
TO
85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CC
- 1.4
V
CC
- 2.0
0.6
Typical
Maximum
V
CC
- 0.9
V
CC
- 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50Ω to V
CC
- 2V.
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= 3.3V±0.3V, T
A
= -40°C
TO
85°C
Symbol
f
CLK
t
PD
tsk(o)
tsk(b)
tsk(pp)
t
S
t
H
t
RR
t
PW
t
R
/ t
F
odc
Parameter
Clock Input Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 5
Bank Skew;
NOTE 3, 5
Bank A
Bank B
nCLK_EN to CLK
CLK to nCLK_EN
CLK
20% to 80%
350
100
400
550
100
48
600
52
CLK to Q (Diff)
1.6
15
10
10
Test Conditions
Minimum
Typical
Maximum
1
2.1
35
20
20
385
Units
GHz
ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
%
Part-to-Part Skew; NOTE 4, 5
Setup Time
Hold Time
Reset Recovery Time
Minimum Pulse Width
Output Rise/Fall Time
Output Duty Cycle
All data taken with outputs ÷4.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points
NOTE 3: Defined as skew within a bank of outputs and with equal load conditions.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
©2016 Integrated Device Technology, Inc
5
Revision B January 25, 2016
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