2.5V Differential LVDS Clock Buffer
ICS854110I
DATA SHEET
General Description
The ICS854110I is a high-performance differential LVDS clock fanout
buffer. The device is designed for signal fanout of high-frequency, low
phase-noise clock signals. The selected differential input signal is
distributed to ten differential LVDS outputs. The ICS854110I is
characterized to operate from a 2.5V power supply. Guaranteed
output-to-output and part-to-part skew characteristics make the
ICS854110I ideal for those clock distribution applications demanding
well-defined performance and repeatability. The device offers an
output slew rate control with four pre-set output transition times to
solve crosstalk and EMI problems in complex board designs. A
fail-safe input design forces the outputs to a defined state if
differential clock inputs are open or shorted, see Table 3D.
Features
•
•
•
•
•
•
•
•
•
•
•
•
Two differential input reference clocks
Differential pair can accept the following differential input levels:
LVPECL, LVDS
Ten LVDS outputs
Maximum clock frequency: 200MHz
Output slew rate control
Fail-safe differential inputs
LVCMOS interface levels for all control inputs
Output skew: 260ps (maximum), for fastest slew rate setting of
0.650 V/ns
Part-to-part skew: 1.2ns (maximum)
Full 2.5V supply voltage
Lead-free (RoHS 6) 32-Lead VFQFN and 32-Lead LQFP package
-40°C to 85°C ambient operating temperature
Block Diagram
Q0
nQ0
Pin Assignments
32 31 30 29 28 27 26 25
ISET
1
2
3
4
5
6
7
8
9
GND
GND
nQ1
nQ0
Q0
Q2
Q1
nQ2
Q7
nQ2
V
DD
24 Q3
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
Pulldown
Q1
nQ1
0
f
REF
CLK_SEL
CLK0
nCLK0
GND
CLK1
nCLK1
nOE
854110AKI
32-Lead VFQFN
5mm x 5mm x 0.925mm
package body
K package
Top View
23 nQ3
22 Q4
21 nQ4
20 Q5
19 nQ5
18 Q6
17 nQ6
Q2
nQ2
Q3
nQ3
Q4
nQ4
1
10 11 12 13 14 15 16
nQ9
nQ8
nQ7
V
DD
Q9
Q8
R
SET
Q6
nQ6
GND
32 31 30 29 28 27 26
ISET
CLK_SEL
CLK0
nCLK0
1
2
3
4
5
6
7
8
9
GND
25
24
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q8
nQ8
Q9
nQ9
854110AYI
32-Lead LQFP
7mm x 7mm x 1.4mm
package body
Y package
Top View
GND
nQ1
nQ0
V
DD
ISET
Slew-Rate
Control
Q0
Q2
Q1
Q5
nQ5
23
22
21
20
19
18
17
GND
CLK1
nCLK1
nOE
nOE
Pulldown
10 11
nQ9
Q9
12 13 14 15 16
nQ7
nQ8
V
DD
Q8
Q7
ICS854110AKI REVISION B JANUARY 27, 2011
1
©2011 Integrated Device Technology, Inc.
ICS854110I Data Sheet
2.5V DIFFERENTIAL LVDS CLOCK BUFFER
Table 1. Pin Descriptions
Number
1
2
3
4
5, 9, 25
6
7
8
10, 11
12, 13
14, 15
16, 32
17, 18
19, 20
21, 22
23, 24
26, 27
28, 29
30, 31
Name
ISET
CLK_SEL
CLK0
nCLK0
GND
CLK1
nCLK1
nOE
nQ9, Q9
nQ8, Q8
nQ7, Q7
V
DD
nQ6, Q6
nQ5, Q5
nQ4, Q4
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
Input
Input
Input
Power
Input
Input
Input
Output
Output
Output
Power
Output
Output
Output
Output
Output
Output
Output
Pulldown
Pulldown
Type
Description
An external fixed resistor (RSET) from this pin to ground is needed to provide a
reference current for setting the slew rate of the differential outputs Q[0:9], nQ[0:9].
See Table 3C for function.
Input clock select. See Table 3A for function. LVCMOS/LVTTL interface levels.
Non-inverting clock/data input 0.
Inverting differential clock input 0.
Power supply ground.
Non-inverting clock/data input 1.
Inverting differential clock input 1.
Output enable. See Table 3B for function. LVCMOS/LVTTL interface levels.
Differential output pair 9. LVDS interface levels.
Differential output pair 8. LVDS interface levels.
Differential output pair 7. LVDS interface levels.
Power supply pins.
Differential output pair 6. LVDS interface levels.
Differential output pair 5. LVDS interface levels.
Differential output pair 4. LVDS interface levels.
Differential output pair 3. LVDS interface levels.
Differential output pair 2. LVDS interface levels.
Differential output pair 1. LVDS interface levels.
Differential output pair 0. LVDS interface levels.
NOTE:
Pulldown
refers to an internal input resistor. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
Parameter
Input Capacitance
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
k
Ω
ICS854110AKI REVISION B JANUARY 27, 2011
2
©2011 Integrated Device Technology, Inc.
ICS854110I Data Sheet
2.5V DIFFERENTIAL LVDS CLOCK BUFFER
Function Tables
Table 3A. CLK_SEL Configuration Table
Input
CLK_SEL
0
1
Operation
CLK0, nCLK0 is the selected reference clock
CLK1, nCLK1 is the selected reference clock
Table 3C. R
SET
Configuration Table
R
SET
Resistor Size (k
Ω
)
4
15
50
150
Typical Output Slew Rate (V/ns)
0.650 (fastest)
0.170
0.150
0.115 (slowest)
NOTE: CLK_SEL is an asynchronous control.
Table 3B. nOE Configuration Table
Input
nOE
0
1
Operation
Outputs Qx, nQx are enabled.
Outputs Qx, nQx are in high-impedance state.
NOTE: The RSET resistor at the ISET pin allows configuration of the
outputs to one of four pre-set output slew rates. A 5% variation of the
RSET resistor size will be tolerated.
NOTE: Slew rates are defined as ±100mV from the center of Q – nQ
signal.
NOTE: OE is an asynchronous control.
Table 3D. Guaranteed Input Fail Safe Operations for CLK0, nCLK0 and CLK1, nCLK1
Input State of Selected Input
Logic Low (Selected Input: CLKx = LOW, nCLKx = HIGH)
Logic High (Selected Input: CLKx = HIGH, nCLKx = LOW)
Inputs Open (Selected Input: CLKx = open, nCLKx = open)
Inputs Shorted (Selected Input: CLKx shorted to nCLKx and tied to V
DD
)
Input Shorted (Selected Input: CLKx shorted to nCLKx and floating)
Outputs Q[0:9], nQ[0:9]
Logic Low (Qx = LOW, nQx = HIGH)
Logic High (Qx = HIGH, nQx = LOW)
Logic High (Qx = HIGH, nQx = LOW)
Logic High (Qx = HIGH, nQx = LOW)
Logic High (Qx = HIGH, nQx = LOW)
ICS854110AKI REVISION B JANUARY 27, 2011
3
©2011 Integrated Device Technology, Inc.
ICS854110I Data Sheet
2.5V DIFFERENTIAL LVDS CLOCK BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
(LVDS)
Continuos Current
Surge Current
Package Thermal Impedance,
θ
JA
32 Lead VFQFN
32 Lead LQFP
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
37.0°C/W (0 mps)
65.7°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
Parameter
Power Supply Voltage
No Load, R
SET
not connected
I
DD
Power Supply Current
All Outputs Loaded, R
SET
= 4k
Ω
No Load, R
SET
= 4k
Ω
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
18
86
30
Units
V
mA
mA
mA
Table 4B. LVCMOS/LVTTL Input DC Characteristics, V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
CLK_SEL, nOE
CLK_SEL, nOE
V
DD
= V
IN
= 2.625V
V
DD
= 2.625V, V
IN
= 0V
-5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
150
Units
V
V
µA
µA
Table 4C. Differential DC Characteristics, V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
PP
V
CMR
Parameter
Peak-to-Peak Input Voltage;
NOTE 1
Common Mode Input Voltage;
NOTE 1, 2
Test Conditions
Minimum
0.15
GND + 0.8
Typical
Maximum
1.2
V
DD
- 0.85
Units
V
V
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as V
IH
.
ICS854110AKI REVISION B JANUARY 27, 2011
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©2011 Integrated Device Technology, Inc.
ICS854110I Data Sheet
2.5V DIFFERENTIAL LVDS CLOCK BUFFER
Table 4D. LVDS DC Characteristics, V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
OD
∆V
OD
V
OS
∆V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
Test Conditions
R
SET
= 4k
Ω
R
SET
= 4k
Ω
R
SET
= 4k
Ω
R
SET
= 4k
Ω
1.115
Minimum
250
Typical
Maximum
600
50
1.430
50
Units
mV
mV
V
mV
AC Electrical Characteristics
Table 5. AC Electrical Characteristics, V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
Parameter
Test Conditions
R
SET
= 4k
Ω
f
REF
Input Frequency
R
SET
= 15k
Ω
R
SET
= 50k
Ω
R
SET
= 150k
Ω
R
SET
= 4k
Ω
f
OUT
Output
Frequency
Q[9:0], nQ[9:0]
R
SET
= 15k
Ω
R
SET
= 50k
Ω
R
SET
= 150k
Ω
t
JIT
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
Section
Propagation
Delay;
NOTE 1
R
SET
= 4k
Ω,
f
REF
= 125MHz,
Integration Range: 12kHz – 20MHz
R
SET
= 4k
Ω
t
PD
CLKx, nCLKx to
any Qx, nQx output
Minimum
Typical
Maximum
200
30
20
16
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ps
200
30
20
16
0.291
3.2
4.6
5.4
7.5
4.0
5.5
6.5
8.3
4.6
6.3
7.7
9.3
ns
ns
ns
ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
V/ns
V/ns
V/ns
V/ns
%
%
%
%
R
SET
= 15k
Ω
R
SET
= 50k
Ω
R
SET
= 150k
Ω
R
SET
= 4k
Ω
R
SET
= 15k
Ω
R
SET
= 50k
Ω
R
SET
= 150k
Ω
R
SET
= 4k
Ω
RSET
≠
4k
Ω
R
SET
= 4k
Ω
125
160
200
240
80
600
825
975
1245
0.450
0.110
0.110
0.075
45
48
48
48
0.650
0.170
0.150
0.115
50
50
50
50
260
425
525
550
185
265
1200
1500
2100
1650
1.3
0.350
0.325
0.250
55
52
52
52
tsk(o)
Output Skew; NOTE 2, 3
tsk(p)
Pulse Skew
tsk(pp)
Part-to-Part Skew; NOTE 3, 4
R
SET
= 15k
Ω
R
SET
= 50k
Ω
R
SET
= 150k
Ω
R
SET
= 4k
Ω
R
SET
= 15k
Ω
R
SET
= 50k
Ω
R
SET
= 150k
Ω
R
SET
= 4k
Ω
, f
REF
≤
200MHz
R
SET
= 15k
Ω
, f
REF
≤
30MHz
R
SET
= 50k
Ω
, f
REF
≤
20MHz
R
SET
= 150k
Ω
, f
REF
≤
16MHz
tsl(o)
Output Clock Slew Rate
odc
Output Duty Cycle; NOTE 5
ICS854110AKI REVISION B JANUARY 27, 2011
5
©2011 Integrated Device Technology, Inc.
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