ISL6263C
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MENDED R
EPLACEM
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DATASHEET
FN6745
Rev 1.00
July 8, 2010
5-Bit VID Single-Phase Voltage Regulator with Current Monitor for GPU Core
Power
The ISL6263C IC is a Single-Phase Synchronous-Buck
PWM voltage regulator for GPU core power application. It
features Intersil’s Robust Ripple Regulator (R
3
)
Technology™. Integrated current monitor, differential remote
sense amplifier, MOSFET driver and bootstrap diode result
in smaller implementation area and lower component cost.
Intersil’s R
3
Technology™ combines the best features of
both fixed-frequency PWM and hysteretic PWM, delivering
excellent light-load efficiency and superior load transient
response by commanding variable switching frequency
during the transitory event. For maximum conversion
efficiency, the ISL6263C automatically enters diode
emulation mode (DEM) when the inductor current attempts
to flow negative. DEM is highly configurable and easy to
set-up. A PWM filter can be enabled, which prevents the
switching frequency from entering the audible spectrum as a
result of extremely light load while in DEM.
The GPU core voltage can be dynamically programmed from
0.41200V to 1.28750V by the five VID input pins without
requiring sequential stepping of the VID states. The
ISL6263C requires only one capacitor for both the soft-start
slew-rate and the dynamic VID slew-rate by internally
connecting the SOFT pin to the appropriate current source.
The voltage Kelvin sensing is accomplished with an
integrated unity-gain true differential amplifier.
Features
• Precise Single-Phase Core Voltage Regulator
- 0.5% System Accuracy 0°C to +100°C
- Differential Remote GPU Die Voltage Sense
• Real-Time GPU Current Monitor Output
• Applications up to 25A
• Input Voltage Range: +5.0V to +25.0V
• Programmable PWM Frequency: 200kHz to 500kHz
• Pre-Biased Output Start-Up Capability
• 5-Bit Voltage Identification Input (VID)
- 0.41200V to 1.28750V
- 25.75mV Steps
- Sequential or Non-Sequential VID Change On-the-Fly
• Configurable PWM Modes
- Forced Continuous Conduction Mode
- Automatic Entry and Exit of Diode Emulation Mode
- Selectable Audible Frequency PWM Filter
• Integrated MOSFET Drivers and Bootstrap Diode
• Choice of Current Sense Schemes
- Lossless Inductor DCR Current Sense
- Precise Resistive Current Sense
• Overvoltage, Undervoltage and Overcurrent Protection
Ordering Information
PART NUMBER
(Notes 2, 3)
ISL6263CHRZ
PART
MARKING
TEMP
RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
• Pb-Free (RoHS Compliant)
Pinout
PGOOD
ISL6263 CHRZ -10 to +100 32 Ld 5x5 QFN L32.5x5
VR_ON
AF_EN
IMON
VID4
NOTES:
1. Please refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-
free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free
peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information
page for
ISL6263C.
For more information on MSL please see techbrief
TB363.
RBIAS
SOFT
OCSET
VW
COMP
FB
VDIFF
VSEN
1
2
3
4
5
6
7
8
32
31
30
29
28
27
VID3
26
25
24 VID1
23 VID0
22 PVCC
VID2
21 LGATE
20 PGND
19 PHASE
18 UGATE
17 BOOT
16
VDD
FDE
ISL6263CHRZ-T ISL6263 CHRZ -10 to +100 32 Ld 5x5 QFN L32.5x5
(Note 1)
ISL6263C
(32 LD 5x5 QFN)
TOP VIEW
THERMAL PAD
(BOTTOM)
9
RTN
10
ICOMP
11
ISN
12
VO
13
ISP
14
VIN
15
VSS
FN6745 Rev 1.00
July 8, 2010
Page 1 of 18
ISL6263C
Absolute Voltage Ratings
VIN to VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +28V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V
PVCC to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V
VSS to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
PHASE to VSS. . . . . . . . . . . . . . . . . . . . . . . . . . (DC) -0.3V to +28V
(<100ns Pulse Width, 10µJ) -5.0V
BOOT to PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V
BOOT to VSS or PGND . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V
UGATE. . . . . . . . . . . . . . . . . . . (DC) -0.3V to PHASE, BOOT +0.3V
(<200ns Pulse Width, 20µJ) -4.0V
LGATE . . . . . . . . . . . . . . . . . . . . (DC) -0.3V to PGND, PVCC +0.3V
(<100ns Pulse Width, 4µJ) -2.0V
ALL Other Pins. . . . . . . . . . . . . . . . . . . . . -0.3V to VSS, VDD +0.3V
Thermal Information
Thermal Resistance (Typical, Notes 4, 5)
JA
(°C/W)
JC
(°C/W)
32 Ld QFN Package. . . . . . . . . . . . . . .
35
6
Junction Temperature Range. . . . . . . . . . . . . . . . . .-55C to +150C
Operating Temperature Range . . . . . . . . . . . . . . . .-10C to +100C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range. . . . . . . . . . . . . . . . . -10°C to +100°C
VIN to VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V to +25V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
PVCC to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
FDE to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +3.3V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
5. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
These specifications apply for T
A
= -10°C to +100°C, unless otherwise stated.
All typical specifications T
A
= +25°C, V
DD
= 5V, PVCC = 5V.
Boldface limits apply over the operating
temperature range, -10°C to +100°C.
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
PARAMETER
VIN
VIN Input Resistance
VIN Shutdown Current
VDD and PVCC
VDD Input Bias Current
VDD Shutdown Current
VDD POR THRESHOLD
Rising VDD POR Threshold Voltage
Falling VDD POR Threshold Voltage
REGULATION
Output Voltage Range
R
VIN
I
VIN_SHDN
VR_ON = 3.3V
VR_ON = 0V, V
IN
= 25V
1.0
1.0
MΩ
µA
I
VDD
I
VDD_SHDN
V
VR_ON = 3.3V
VR_ON = 0V, V
DD
= 5.0V
2.7
3.3
1.0
mA
µA
VDD_THR
VDD_THF
4.35
3.85
4.10
4.50
V
V
V
V
OUT_MAX
OUT_MIN
VID<4:0> = 00000
VID<4:0> = 11111
VID<4:0> = 00000 to 11110 (1.28750V
to 0.51500V)
VID<4:0> = 11110 to 11111 (0.51500V to
0.41200V)
1.28750
0.41200
25.75
103
-0.5
-1.0
-3.0
0.5
1.0
3.0
V
V
mV/step
mV
%
%
%
V
VID Voltage Step
System Accuracy
VID = 1.28750V to 0.74675V
T
A
= 0°C to +100°C
VID = 0.72100V to 0.51500V
T
A
= 0°C to +100°C
VID = 0.41200
T
A
= 0°C to +100°C
FN6745 Rev 1.00
July 8, 2010
Page 5 of 18