Freescale Semiconductor
Data Sheet: Technical Data
Document Number: IMX51CEC
Rev. 6,
10/2012
IMX51
i.MX51 Applications
Processors for Consumer and
Industrial Products
Package Information
Plastic Package
Case 2058 13 x 13 mm, 0.5 mm pitch
Case 2017 19 x 19 mm, 0.8 mm pitch
Ordering Information
See
Table 1
on
page 3
for ordering information.
1
Introduction
The i.MX51 multimedia applications processors
represent Freescale Semiconductor’s latest addition to a
growing family of multimedia-focused products that
offer high performance processing and are optimized for
lowest power consumption.
The i.MX51 processors feature Freescale’s advanced and
power-efficient implementation of the ARM
Cortex™-A8 core, which operates at speeds as high as
800 MHz. Up to 200 MHz DDR2 and mobile DDR
DRAM clock rates are supported. These devices are
suitable for applications such as the following:
• Netbooks (web tablets)
• Nettops (Internet desktop devices)
• Mobile Internet devices (MID)
• Portable media players (PMP)
• Portable navigation devices (PND)
• High-end PDAs
• Gaming consoles
• Automotive navigation and entertainment (see
automotive data sheet, IMX51AEC)
© 2012 Freescale Semiconductor, Inc. All rights reserved.
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 3
1.2. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1. Special Signal Considerations . . . . . . . . . . . . . . . 12
3. IOMUX Configuration for Boot Media . . . . . . . . . . . . . . . 14
3.1. NAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2. SD/MMC IOMUX Pin Configuration . . . . . . . . . . . 15
3.3. I
2
C IOMUX Pin Configuration . . . . . . . . . . . . . . . . 15
3.4. eCSPI/CSPI IOMUX Pin Configuration . . . . . . . . 16
3.5. Wireless External Interface Module (WEIM) . . . . 16
3.6. UART IOMUX Pin Configuration . . . . . . . . . . . . . 16
3.7. USB-OTG IOMUX Pin Configuration . . . . . . . . . . 16
4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1. Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . 17
4.2. Supply Power-Up/Power-Down Requirements and
Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.3. I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 24
4.4. Output Buffer Impedance Characteristics . . . . . . 31
4.5. I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 35
4.6. Module Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.7. External Peripheral Interfaces . . . . . . . . . . . . . . . 74
5. Package Information and Contact Assignments . . . . . 153
5.1. 13 x 13 mm Package Information . . . . . . . . . . . . 153
5.2. 19 x 19 mm Package Information . . . . . . . . . . . . 173
5.3. 13
×
13 mm, 0.5 Pitch Ball Map . . . . . . . . . . . . . 191
5.4. 19 x 19 mm, 0.8 Pitch Ball Map . . . . . . . . . . . . . 195
6. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Introduction
Features include the following:
•
Smart Speed Technology—The
heart of the i.MX51 processors is a level of power management
throughout the device that enables the rich suite of multimedia features and peripherals to achieve
minimum system power consumption in both active and various low-power modes. Smart Speed
Technology enables the designer to deliver a feature-rich product that requires levels of power that
are far less than typical industry expectations.
•
Applications Processor—The
i.MX51 processors boost the capabilities of high-tier portable
applications by providing for the ever-increasing MIPS needs of operating systems and games.
Freescale’s Dynamic Voltage and Frequency Scaling (DVFS) allows the device run at much lower
voltage and frequency with sufficient MIPS for tasks such as audio decode resulting in significant
power reduction.
•
Multimedia Powerhouse—The
multimedia performance of the i.MX51 processors is boosted by
a multi-level cache system and further enhanced by a Multi-Standard Hardware Video Codec,
autonomous Image Processing Unit, SD and HD720p Triple Video (TV) Encoder with triple video
DAC, Neon (including Advanced SIMD, 32-bit Single-Precision floating point support and Vector
Floating Point co-processor), and a programmable smart DMA (SDMA) controller.
•
Powerful Graphics Acceleration—Graphics
is the key to mobile game navigation, web browsing,
and other applications. The i.MX51 processors provide two independent, integrated Graphics
Processing Units: OpenGL ES 2.0 3D graphics accelerator (27 Mtri/s, 166 Mpix/s) and
OpenVG 1.1 2D graphics accelerator (166 Mpix/s).
•
Interface Flexibility—The
i.MX51 processor interface supports connection to all popular types of
external memories: DDR2, Mobile DDR, NOR Flash, PSRAM, Cellular RAM, NAND Flash
(MLC and SLC), and OneNAND. Designers seeking to provide products that deliver a rich
multimedia experience find a full suite of on-chip peripherals: LCD controller and CMOS sensor
interface, High-Speed USB On-The-Go with PHY, and three High-Speed USB hosts, multiple
expansion card ports (High-Speed MMC/SDIO Host and others), 10/100 Ethernet controller, and
a variety of other popular interfaces (PATA, UART, I
2
C, I
2
S serial audio, and SIM card, among
others).
•
Increased Security—Because
the need for advanced security for mobile devices continues to
increase, the i.MX51 processors deliver hardware-enabled security features that enable secure
e-commerce, digital rights management (DRM), information encryption, secure boot, and secure
software downloads. For detailed information about the MX51 security features contact your
Freescale representative.
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 6
2
Freescale Semiconductor
Introduction
1.1
Ordering Information
Table 1. Ordering Information
1
2,
Table 1
provides the ordering information.
Part Number
Mask Set
Features
Case
Temperature
Range (
°
C)
–40 to 95
–20 to 85
–40 to 95
–20 to 85
–40 to 95
–20 to 85
–20 to 85
Package
3
MCIMX512CJM6C
MCIMX512DJM8C
MCIMX513CJM6C
MCIMX513DJM8C
MCIMX515CJM6C
MCIMX515DJM8C
MCIMX515DVK8C!
1
M77X
M77X
M77X
M77X
M77X
M77X
M77X
No hardware video codecs
No hardware graphics accelerators
No hardware video codecs
No hardware graphics accelerators
No hardware graphics accelerators
No hardware graphics accelerators
Full specification
Full specification
Full specification
19 x 19 mm, 0.8 mm pitch BGA
Case 2017
19 x 19 mm, 0.8 mm pitch BGA
Case 2017
19 x 19 mm, 0.8 mm pitch BGA
Case 2017
19 x 19 mm, 0.8 mm pitch BGA
Case 2017
19 x 19 mm, 0.8 mm pitch BGA
Case 2017
19 x 19 mm, 0.8 mm pitch BGA
Case 2017
13 x 13 mm, 0.5 mm pitch BGA
Case 2058
For Junction Temperature (Tj) maximum ratings, see
Table 11, "Absolute Maximum Ratings," on page 18.
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010:
Indicated by the Icon (!)
3
Case 2017 and Case 2058 are RoHS compliant, lead-free, MSL = 3.
2
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 6
Freescale Semiconductor
3
Introduction
1.2
Block Diagram
TV-Out
Access.
Conn.
Figure 1
shows the functional modules of the processor.
Digital
Audio
DDR
Memory
NOR/Nand Battery Ctrl
Device
Flash
USB
Dev/Host
Camera 1
Camera 2
LCD Display 1
LCD Display 2
ATA HDD
External
Memory I/F
USB PHY
Application Processor Domain (AP)
TV Encoder
USB OTG +
3 HS Ports
Smart DMA
(SDMA)
Ethernet
GPS
RF/IF ICs
SIM
Audio/Power
Management
JTAG
IrDA
XVR
Bluetooth
Fuse Box
Image Processing
Subsystem
AP Peripherals
eCSPI
(2
)
CSPI
UART (3)
AUDMUX
SPBA
AXI and AHB Switch Fabric
Internal
RAM
(128 Kbytes)
Boot
ROM
ARM Cortex A8
Platform
ARM Cortex A8
Neon and VFP
I
2
C(2),HSI
2
C
1-WIRE
PWM (2)
IIM
IOMUXC
KPP
GPIOx32 (4)
SJC
SSI (3)
FIRI
Debug
DAP
TPIU
CTI (2)
SDMA Peripherals
eSDHC (4)
UART
SPDIF Tx
FEC
SSI
eCSPI
(1 of 2)
SIM
P-ATA
L1 I/D cache
L2 cache
ETM, CTI0,1
Security
SAHARA
Lite
RTIC
SCC
SRTC
CSU
TZIC
Timers
WDOG (2)
GPT
EPIT (2)
Video
Proc. Unit
(VPU)
3D Graphics
Proc Unit
(GPU)
Graphics
Memory
(128 Kbytes)
2D Graphics
Proc Unit
(GPU2D)
Clock and Reset
PLL (3)
CCM
GPC
SRC
XTALOSC
CAMP (2)
WLAN
USB-OTG
XVR
MMC/SDIO
Keypad
Figure 1. Functional Block Diagram
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 6
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Freescale Semiconductor
Features
2
Features
Table 2. i.MX51 Digital and Analog Modules
The i.MX51 processor contains a large number of digital and analog modules that are described in
Table 2.
Block
Mnemonic
1-WIRE
ARM
Cortex™-A8
Block Name
1-Wire
Interface
ARM
Cortex™-A8
Platform
Subsystem
Connectivity
Peripherals
ARM
Brief Description
1-Wire support provided for interfacing with an on-board EEPROM, and smart
battery interfaces, for example: Dallas DS2502.
The ARM Cortex™-A8 Core Platform consists of the ARM Cortex™-A8
processor version r2p5 (with TrustZone) and its essential sub-blocks. It contains
the Level 2 Cache Controller, 32 Kbyte L1 instruction cache, 32 Kbyte L1 data
cache, and a 256 Kbyte L2 cache. The platform also contains an Event Monitor
and Debug modules. It also has a NEON co-processor with SIMD media
processing architecture, register file with 32
×
64-bit general-purpose registers,
an Integer execute pipeline (ALU, Shift, MAC), dual, single-precision floating
point execute pipeline (FADD, FMUL), load/store and permute pipeline and a
Non-Pipelined Vector Floating Point (VFP) co-processor (VFPv3).
The elements of the audio subsystem are three Synchronous Serial Interfaces
(SSI1-3), a Digital Audio Mux (AUDMUX), and Digital Audio Out (SPDIF TX).
See the specific interface listings in this table.
The AUDMUX is a programmable interconnect for voice, audio, and
synchronous data routing between host serial interfaces (for example, SSI1,
SSI2, and SSI3) and peripheral serial interfaces (audio and voice codecs). The
AUDMUX has seven ports (three internal and four external) with identical
functionality and programming models. A desired connectivity is achieved by
configuring two or more AUDMUX ports.
Audio
Subsystem
AUDMUX
Audio
Subsystem
Digital Audio
Mux
Multimedia
Peripherals
Multimedia
Peripherals
CCM
GPC
SRC
CSPI-1,
eCSPI-2
eCSPI-3
CSU
These modules are responsible for clock and reset distribution in the system,
Clock Control Clocks,
and also for system power management. The modules include three PLLs and
Resets, and
Module
Global Power Power Control a Frequency Pre-Multiplier (FPM).
Controller
System Reset
Controller
Configurable
SPI,
Enhanced
CSPI
Central
Security Unit
Connectivity
Peripherals
Full-duplex enhanced Synchronous Serial Interface, with data rate up to
66.5 Mbit/s (for eCSPI, master mode). It is configurable to support Master/Slave
modes, four chip selects to support multiple peripherals.
The Central Security Unit (CSU) is responsible for setting comprehensive
security policy within the i.MX51 platform, and for sharing security information
between the various security modules. The Security Control Registers (SCR) of
the CSU are set during boot time by the High Assurance Boot (HAB) code and
are locked to prevent further writing.
The Debug System provides real-time trace debug capability of both instructions
and data. It supports a trace protocol that is an integral part of the ARM Real
Time Debug solution (RealView). Real-time tracing is controlled by specifying a
set of triggering and filtering resources, which include address and data
comparators, cross-system triggers, counters, and sequencers.
Security
Debug
System
Debug
System
System
Control
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 6
Freescale Semiconductor
5
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