MC74HC595A
8-Bit Serial-Input/Serial or
Parallel-Output Shift
Register with Latched
3-State Outputs
High−Performance Silicon−Gate CMOS
The MC74HC595A consists of an 8−bit shift register and an 8−bit
D−type latch with three−state parallel outputs. The shift register
accepts serial data and provides a serial output. The shift register also
provides parallel data to the 8−bit latch. The shift register and latch
have independent clock inputs. This device also has an asynchronous
reset for the shift register.
The HC595A directly interfaces with the SPI serial data port on
CMOS MPUs and MCUs.
Features
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MARKING
DIAGRAMS
16
16
1
PDIP−16
N SUFFIX
CASE 648
1
16
16
1
SOIC−16
D SUFFIX
CASE 751B
1
16
TSSOP−16
DT SUFFIX
CASE 948F
1
A
WL, L
YY, Y
WW, W
G,
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
HC
595A
ALYWG
G
HC595AG
AWLYWW
MC74HC595AN
AWLYYWWG
•
•
•
•
•
•
•
•
•
•
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC
Standard No. 7 A
Chip Complexity: 328 FETs or 82 Equivalent Gates
Improvements over HC595
−
Improved Propagation Delays
−
50% Lower Quiescent Power
−
Improved Input Noise and Latchup Immunity
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free and are RoHS Compliant
16
1
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
©
Semiconductor Components Industries, LLC, 2013
July, 2013
−
Rev. 15
1
Publication Order Number:
MC74HC595A/D
MC74HC595A
LOGIC DIAGRAM
SERIAL
DATA
INPUT
A
14
15
1
2
3
SHIFT
REGISTER
4
LATCH
5
6
7
SHIFT 11
CLOCK
10
RESET
LATCH 12
CLOCK
OUTPUT 13
ENABLE
Q
A
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
PARALLEL
DATA
OUTPUTS
PIN ASSIGNMENT
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
Q
A
A
OUTPUT ENABLE
LATCH CLOCK
SHIFT CLOCK
RESET
SQ
H
9
SQ
H
SERIAL
DATA
OUTPUT
V
CC
= PIN 16
GND = PIN 8
ORDERING INFORMATION
Device
MC74HC595ANG
MC74HC595ADG
NLV74HC595ADG*
MC74HC595ADR2G
NLV74HC595ADR2G*
MC74HC595ADTR2G
NLV74HC595ADTR2G*
MC74HC595ADTG
Package
PDIP−16
(Pb−Free)
SOIC−16
(Pb−Free)
SOIC−16
(Pb−Free)
2500 Tape & Reel
TSSOP−16
(Pb−Free)
TSSOP−16
(Pb−Free)
96 Units / Tube
Shipping
†
500 Units / Rail
48 Units / Rail
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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2
MC74HC595A
MAXIMUM RATINGS
Symbol
V
CC
V
in
V
out
I
in
I
out
I
CC
P
D
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air,
Plastic DIP†
SOIC Package†
TSSOP Package†
Value
–0.5 to +7.0
–0.5 to V
CC
+0.5
–0.5 to V
CC
+0.5
±20
±35
±75
750
500
450
–65 to +150
260
>3000
>400
N/A
Unit
V
V
V
mA
mA
mA
mW
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND
v
(V
in
or V
out
)
v
V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
T
stg
T
L
V
ESD
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
ESD Withstand Voltage Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
_C
_C
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package:
−
6.1 mW/_C from 65_ to 125_C
1. Tested to EIA/JESD22−A114−A.
2. Tested to EIA/JESD22−A115−A.
3. Tested to JESD22−C101−A.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
in
, V
out
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage
(Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time
(Figure 1)
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Min
2.0
0
– 55
0
0
0
Max
6.0
V
CC
+ 125
1000
500
400
Unit
V
V
_C
ns
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Symbol
V
IH
Parameter
Minimum High−Level Input
Voltage
Test Conditions
V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
|
v
20
mA
V
CC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
4.5
6.0
|I
out
|
v
2.4 mA
|I
out
|
v
6.0 mA
|I
out
|
v
7.8 mA
3.0
4.5
6.0
Guaranteed Limit
– 55 to 25_C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.48
3.98
5.48
v
85_C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.34
3.84
5.34
v
125_C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.2
3.7
5.2
Unit
V
V
IL
Maximum Low−Level Input
Voltage
V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
|
v
20
mA
V
V
OH
Minimum High−Level Output
Voltage, Q
A
−
Q
H
V
in
= V
IH
or V
IL
|I
out
|
v
20
mA
V
in
= V
IH
or V
IL
V
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3
MC74HC595A
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Symbol
V
OL
Parameter
Maximum Low−Level Output
Voltage, Q
A
−
Q
H
Test Conditions
V
in
= V
IH
or V
IL
|I
out
|
v
20
mA
V
in
= V
IH
or V
IL
|I
out
|
v
2.4 mA
|I
out
|
v
6.0 mA
|I
out
|
v
7.8 mA
V
CC
V
2.0
4.5
6.0
3.0
4.5
6.0
2.0
4.5
6.0
|I
out
|
v
2.4 mA
II
out
I
v
4.0 mA
II
out
Iv 5.2 mA
3.0
4.5
6.0
2.0
4.5
6.0
|I
out
|
v
2.4 mA
II
out
I
v
4.0 mA
II
out
Iv 5.2 mA
3.0
4.5
6.0
6.0
6.0
Guaranteed Limit
– 55 to 25_C
0.1
0.1
0.1
0.26
0.26
0.26
1.9
4.4
5.9
2.48
3.98
5.48
0.1
0.1
0.1
0.26
0.26
0.26
±
0.1
±
0.5
v
85_C
0.1
0.1
0.1
0.33
0.33
0.33
1.9
4.4
5.9
2.34
3.84
5.34
0.1
0.1
0.1
0.33
0.33
0.33
±
1.0
±
5.0
v
125_C
0.1
0.1
0.1
0.4
0.4
0.4
1.9
4.4
5.9
2.2
3.7
5.2
0.1
0.1
0.1
0.4
0.4
0.4
±
1.0
±
10
mA
mA
V
V
Unit
V
V
OH
Minimum High−Level Output
Voltage, SQ
H
V
in
= V
IH
or V
IL
II
out
I
v
20
mA
V
in
= V
IH
or V
IL
V
OL
Maximum Low−Level Output
Voltage, SQ
H
V
in
= V
IH
or V
IL
II
out
I
v
20
mA
V
in
= V
IH
or V
IL
I
in
I
OZ
Maximum Input Leakage
Current
Maximum Three−State
Leakage
Current, Q
A
−
Q
H
Maximum Quiescent Supply
Current (per Package)
V
in
= V
CC
or GND
Output in High−Impedance State
V
in
= V
IL
or V
IH
V
out
= V
CC
or GND
V
in
= V
CC
or GND
l
out
= 0
mA
I
CC
6.0
4.0
40
160
mA
AC ELECTRICAL CHARACTERISTICS
(C
L
= 50 pF, Input t
r
= t
f
= 6.0 ns)
Symbol
f
max
Parameter
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 7)
V
CC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
Guaranteed Limit
– 55 to 25_C
6.0
15
30
35
140
100
28
24
145
100
29
25
140
100
28
24
150
100
30
26
135
90
27
23
v
85_C
4.8
10
24
28
175
125
35
30
180
125
36
31
175
125
35
30
190
125
38
33
170
110
34
29
v
125_C
4.0
8.0
20
24
210
150
42
36
220
150
44
38
210
150
42
36
225
150
45
38
205
130
41
35
Unit
MHz
t
PLH
,
t
PHL
Maximum Propagation Delay, Shift Clock to SQ
H
(Figures 1 and 7)
ns
t
PHL
Maximum Propagation Delay, Reset to SQ
H
(Figures 2 and 7)
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Latch Clock to Q
A
−
Q
H
(Figures 3 and 7)
ns
t
PLZ
,
t
PHZ
Maximum Propagation Delay, Output Enable to Q
A
−
Q
H
(Figures 4 and 8)
ns
t
PZL
,
t
PZH
Maximum Propagation Delay, Output Enable to Q
A
−
Q
H
(Figures 4 and 8)
ns
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4
MC74HC595A
AC ELECTRICAL CHARACTERISTICS
(C
L
= 50 pF, Input t
r
= t
f
= 6.0 ns)
Symbol
t
TLH
,
t
THL
Parameter
Maximum Output Transition Time, Q
A
−
Q
H
(Figures 3 and 7)
V
CC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
—
—
Guaranteed Limit
– 55 to 25_C
60
23
12
10
75
27
15
13
10
15
v
85_C
75
27
15
13
95
32
19
16
10
15
v
125_C
90
31
18
15
110
36
22
19
10
15
Unit
ns
t
TLH
,
t
THL
Maximum Output Transition Time, SQ
H
(Figures 1 and 7)
ns
C
in
C
out
Maximum Input Capacitance
Maximum Three−State Output Capacitance (Output in
High−Impedance State), Q
A
−
Q
H
pF
pF
Typical @ 25°C, V
CC
= 5.0 V
C
PD
Power Dissipation Capacitance (Per Package)*
300
pF
TIMING REQUIREMENTS
(Input t
r
= t
f
= 6.0 ns)
Symbol
t
su
Parameter
Minimum Setup Time, Serial Data Input A to Shift Clock
(Figure 5)
V
CC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
Guaranteed Limit
25_C to –55_C
50
40
10
9.0
75
60
15
13
5.0
5.0
5.0
5.0
50
40
10
9.0
60
45
12
10
50
40
10
9.0
50
40
10
9.0
1000
800
500
400
v
85_C
65
50
13
11
95
70
19
16
5.0
5.0
5.0
5.0
65
50
13
11
75
60
15
13
65
50
13
11
65
50
13
11
1000
800
500
400
v
125_C
75
60
15
13
110
80
22
19
5.0
5.0
5.0
5.0
75
60
15
13
90
70
18
15
75
60
15
13
75
60
15
13
1000
800
500
400
Unit
ns
t
su
Minimum Setup Time, Shift Clock to Latch Clock
(Figure 6)
ns
t
h
Minimum Hold Time, Shift Clock to Serial Data Input A
(Figure 5)
ns
t
rec
Minimum Recovery Time, Reset Inactive to Shift Clock
(Figure 2)
ns
t
w
Minimum Pulse Width, Reset
(Figure 2)
ns
t
w
Minimum Pulse Width, Shift Clock
(Figure 1)
ns
t
w
Minimum Pulse Width, Latch Clock
(Figure 6)
ns
t
r
, t
f
Maximum Input Rise and Fall Times
(Figure 1)
ns
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