2.5v/3.3v Differential LVPECL 1:9
Clock Distribution Buffer and Clock Driver
Product Discontinuance Notice – Last Time Buy Expires on (12/7/2013)
MC100ES6226
DATASHEET
The MC100ES6226 is a bipolar monolithic differential clock distribution buffer and clock
divider. Designed for most demanding clock distribution systems, the MC100ES6226
supports various applications requiring a large number of outputs to drive precisely aligned
clock signals. Using SiGe technology and a fully differential architecture, the device offers
superior digital signal characteristics and very low clock skew error. Target applications for
this clock driver are high performance clock distribution systems for computing,
networking and telecommunication systems.
Features
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•
•
•
•
•
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Fully differential architecture from input to all outputs
SiGe technology supports near-zero output skew
Selectable 1:1 or 1:2 frequency outputs
LVPECL compatible differential clock inputs and outputs
LVCMOS compatible control inputs
Single 3.3V or 2.5V supply
Max. 35ps maximum output skew (within output bank)
Max. 50ps maximum device skew
Supports DC operation and up to 3GHz (typ.) clock signals
Synchronous output enable eliminating output runt pulse generation and metastability
Standard 32-lead LQFP package
Industrial temperature range (-40°C TO 85°C)
32-lead Pb-free package available
2.5 V/3.3 V DIFFERENTIAL
LVPECL 1:9 CLOCK DISTRIBUTION
BUFFER AND CLOCK DIVIDER
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-03
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-03
Functional Description
MC100ES6226 is designed for very skew critical differential clock distribution systems
and supports clock frequencies from DC up to 3.0GHz. Typical applications for the
MC100ES6226 are primary clock distribution systems on backplanes of high-performance
computer, networking and telecommunication systems, as well as on-board clocking of
OC-3, OC-12 and OC-48 speed communication systems.
The MC100ES6226 can be operated from a 3.3V or 2.5V positive supply without the
requirement of a negative supply line. Each of the output banks of three differential clock
output pairs may be independently configured to distribute the input frequency or half of
the input frequency. The FSEL0 and FSEL1 clock frequency selects are asynchronous
control inputs. Any changes of the control inputs require a MR pulse for re-synchronization
of the
2
outputs.
ORDERING INFORMATION
Device
MC100ES6226FA
MC100ES6226FAR2
MC100ES6226AC
MC100ES6226ACR2
Package
LQFP-32
LQFP-32
LQFP-32 (Pb-Free)
LQFP-32 (Pb-Free)
MC100ES6226 DECEMBER 18, 2012
1
©2012 Integrated Device Technology, Inc.
MC100ES6226 Data Sheet
2.5V/3.3V DIFFERENTIAL LVPECL 1:9 CLOCK DISTRIBUTION BUFFER AND CLOCK DRIVER
V
CC
CLK
CLK
BANK A
1
2
BANK B
QA0
QA0
QA1
QA1
QA2
QA2
QB0
QB0
QB1
QB1
QB2
QB2
MR
FSEL0
FSEL1
BANK C
QC0
QC0
QC1
QC1
QC2
QC2
OE
Sync
Figure 1. MC100ES6226 Logic Diagram
QB0
QB0
QB1
QB1
QB2
QB2
18
V
CC
24
QA2
QA2
V
CC
QA1
QA1
QA0
QA0
V
CC
25
26
27
28
29
30
31
32
1
23
22
21
20
19
V
CC
17
16
15
14
QC0
QC0
QC1
QC1
VCC
QC2
QC2
V
CC
13
12
11
10
9
8
MR
MC100ES6226
2
3
4
5
6
7
FSEL0
FSEL1
GND
CLK
CLK
V
CC
Figure 2. 32-Lead Package Pinout
(Top View)
MC100ES6226 REVESION 5 DECEMBER 18, 2012
2
OE
©2012 Integrated Device Technology, Inc.
MC100ES6226 Data Sheet
2.5V/3.3V DIFFERENTIAL LVPECL 1:9 CLOCK DISTRIBUTION BUFFER AND CLOCK DRIVER
Table 1. Pin Configuration
Pin
CLK, CLK
OE
MR
FSEL0, FSEL1
QA[0-2], QA[0–2]
QB[0-2], QB[0–2]
QC[0-2], QC[0–2]
GND
V
CC
Input
Input
Input
Input
Output
I/O
Type
LVPECL
LVCMOS
LVCMOS
LVCMOS
LVPECL
Differential reference clock signal input
Output enable
Device reset
Output frequency divider select
Differential clock outputs (banks A, B and C)
Function
Supply
Supply
GND
V
CC
Negative power supply
Positive power supply. All V
CC
pins must be connected to the positive power supply for
correct DC and AC operation
Table 2. Function Table
Control
OE
Default
0
0
1
Qx[0–2], Qx[0–2] are active. Deassertion of OE can be Qx[0–2] = L, Qx[0–2] =H (outputs disabled). Assertion
asynchronous to the reference clock without generation of OE can be asynchronous to the reference clock
of output runt pulses
without generation of output runt pulses
Normal operation
See
Table 3
Device reset (asynchronous)
MR
FSEL0, FSEL1
0
00
Table 3. Output Frequency Select Control
FSEL0
0
0
1
1
FSEL1
0
1
0
1
QA0 to QA2
f
QA0:2
= f
CLK
f
QA0:2
= f
CLK
f
QA0:2
= f
CLK
f
QA0:2
= f
CLK
2
QB0 to QB2
f
QB0:2
= f
CLK
f
QB0:2
= f
CLK
f
QB0:2
= f
CLK
2
f
QB0:2
= f
CLK
2
QC0 to QC2
f
QC0:2
= f
CLK
f
QC0:2
= f
CLK
2
f
QC0:2
= f
CLK
2
f
QC0:2
= f
CLK
2
Table 4. Absolute Maximum Ratings
(1)
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
T
S
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage Temperature
–65
Characteristics
Min
–0.3
–0.3
–0.3
Max
3.6
V
CC
+0.3
V
CC
+0.3
20
50
125
Unit
V
V
V
mA
mA
C
Condition
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied.
MC100ES6226 REVESION 5 DECEMBER 18, 2012
3
©2012 Integrated Device Technology, Inc.
MC100ES6226 Data Sheet
2.5V/3.3V DIFFERENTIAL LVPECL 1:9 CLOCK DISTRIBUTION BUFFER AND CLOCK DRIVER
Table 5. General Specifications
Symbol
V
TT
MM
HBM
CDM
LU
C
IN
JA
Thermal Resistance Junction to Ambient
JESD 51-3, single layer test board
Characteristics
Output Termination Voltage
ESD Protection (Machine Model)
ESD Protection (Human Body Model)
ESD Protection (Charged Device Model)
Latch-Up Immunity
300
4000
2000
200
4.0
83.1
73.3
68.9
63.8
57.4
59.0
54.4
52.5
50.4
47.8
23.0
0
86.0
75.4
70.9
65.3
59.6
60.6
55.7
53.8
51.5
48.8
26.3
110
Min
Typ
V
CC
– 2
(1)
Max
Unit
V
V
V
V
mA
pF
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C
Inputs
Natural convection
100 ft/min
200 ft/min
400 ft/min
800 ft/min
Natural convection
100 ft/min
200 ft/min
400 ft/min
800 ft/min
MIL-SPEC 883E
Method 1012.1
Condition
JESD 51-6, 2S2P multilayer test board
JC
Thermal Resistance Junction to Case
Operating Junction Temperature
(2)
(continuous operation)
MTBF = 9.1 years
1. Output termination voltage V
TT
= 0V for V
CC
= 2.5V operation is supported but the power consumption of the device will increase.
2. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according to the
application life time requirements (See application note AN1545 for more information). The device AC and DC parameters are specified up to 110°C
junction temperature allowing the MC100ES6226 to be used in applications requiring industrial temperature range. It is recommended that users of
the MC100ES6226 employ thermal modeling analysis to assist in applying the junction temperature specifications to their particular application.
MC100ES6226 REVESION 5 DECEMBER 18, 2012
4
©2012 Integrated Device Technology, Inc.
MC100ES6226 Data Sheet
2.5V/3.3V DIFFERENTIAL LVPECL 1:9 CLOCK DISTRIBUTION BUFFER AND CLOCK DRIVER
Table 6. DC Characteristics
(V
CC
= 3.3V ± 5% and 2.5V ± 5%, T
J
= 0°C to +110°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
LVCMOS Control Inputs (OE, FSEL0, FSEL1, MR)
V
IL
V
IH
I
IN
V
PP
V
CMR
V
IH
V
IL
I
IN
V
OH
V
OL
I
GND
I
CC
1.
2.
3.
4.
Input Voltage Low
Input Voltage High
Input Current
(1)
DC Differential Input Voltage
(3)
Differential Cross Point Voltage
(4)
Input High Voltage
Input Low Voltage
Input Current
V
CC
= 3.3V
V
CC
= 2.5V
V
CC
= 3.3V
V
CC
= 2.5V
2.2
1.7
150
0.8
0.7
V
V
A
V
IN
= V
CC
or V
IN
= GND
Differential operation
Differential operation
LVPECL Clock Inputs (CLK, CLK)
(2)
0.1
1.0
TBD
TBD
1.3
V
CC
– 0.3
TBD
TBD
150
A
V
IN
= TBD or V
IN
= TBD
Termination 50
to V
TT
Termination 50
to V
TT
GND pin
All V
CC
pins
V
V
LVPECL Clock Outputs (QA[2:0], QB[2:0], QC[2:0])
Output High Voltage
Output Low Voltage
V
CC
– 1.1
V
CC
– 1.8
65
325
V
CC
– 0.8
V
CC
– 1.4
110
400
V
V
Supply Current
Maximum Quiescent Supply Current without
Output Termination Current
Maximum Quiescent Supply Current with
Output Termination Current
mA
mA
Input have internal pullup/pulldown resistors which affect the input current.
Clock inputs driven by LVPECL compatible signals.
V
PP
is the minimum differential input voltage swing required to maintain AC characteristic.
V
CMR
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
CMR
(DC) range and the
input swing lies within the V
PP
(DC) specification.
MC100ES6226 REVESION 5 DECEMBER 18, 2012
5
©2012 Integrated Device Technology, Inc.
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