MC10ELT25, MC100ELT25
-5 V Differential ECL to TTL
Translator
Description
The MC10ELT/100ELT25 is a differential ECL to TTL translator.
Because ECL levels are used, a +5 V, −5.2 V (or −4.5 V) and ground
are required. The small outline 8-lead package and the single gate of
the ELT25 makes it ideal for those applications where space,
performance and low power are at a premium.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01
mF
capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
The 100 Series contains temperature compensation.
Features
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MARKING DIAGRAMS*
8
1
SOIC−8
D SUFFIX
CASE 751
1
8
HLT25
ALYW
G
1
8
KLT25
ALYW
G
•
•
•
•
•
8
1
TSSOP−8
DT SUFFIX
CASE 948R
8
HT25
ALYWG
G
8
KT25
ALYWG
G
2.6 ns Typical Propagation Delay
100 MHz F
MAX
CLK
24 mA TTL Outputs
Flow Through Pinouts
Operating Range: V
CC
= 4.5 V to 5.5 V with GND = 0 V;
V
EE
= −4.2 V to −5.7 V with GND = 0 V
•
Internal Input 50 KW Pulldown Resistors
•
Q Output will default HIGH with inputs open or < 1.3 V
•
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
1
1
1
DFN8
MN SUFFIX
CASE 506AA
H
K
5F
2U
M
= MC10
= MC100
= MC10
= MC100
= Date Code
A
L
Y
W
G
5F MG
G
4
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
©
Semiconductor Components Industries, LLC, 2015
1
August, 2015 − Rev. 14
Publication Order Number:
MC10ELT25/D
2U MG
G
4
MC10ELT25, MC100ELT25
V
EE
D
1
TTL
ECL
D
3
6
NC
8
V
CC
Q
Table 1. PIN DESCRIPTION
Pin
D, D
Q
V
BB
V
CC
V
EE
Function
ECL Differential Inputs
TTL Output
Reference Voltage Output
Positive Supply
Negative Supply
Ground
No Connect
(DFN8 only) Thermal exposed pad must be con-
nected to a sufficient thermal conduit. Electric-
ally connect to the most negative supply (GND)
or leave unconnected, floating open.
2
7
V
BB
4
5
GND
GND
NC
Figure 1. 8−Lead Pinout
(Top View)
and Logic
Diagram
EP
Table 2. ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Human Body Model
Machine Model
Value
75 kW
N/A
> 1 kV
> 400 V
Pb−Free Pkg
Level 1
Level 3
Level 1
UL 94 V−0 @ 0.125 in
38 Devices
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
SOIC−8
TSSOP−8
DFN8
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Oxygen Index: 28 to 34
Table 3. MAXIMUM RATINGS
Symbol
V
CC
V
EE
V
IN
I
BB
T
A
T
stg
q
JA
q
JC
q
JA
q
JC
q
JA
T
sol
q
JC
Parameter
Positive Power Supply
Negative Power Supply
Input Voltage
V
BB
Sink/Source
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Thermal Resistance (Junction−to−Ambient)
Wave Solder
Pb−Free
0 lfpm
500 lfpm
Standard Board
0 lfpm
500 lfpm
Standard Board
0 lfpm
500 lfpm
<2 to 3 sec @ 260°C
(Note 2)
DFN8
SOIC−8
SOIC−8
SOIC−8
TSSOP−8
TSSOP−8
TSSOP−8
DFN8
DFN8
Condition 1
GND = 0 V
GND = 0 V
GND = 0 V
Condition 2
V
EE
= −5.0 V
V
CC
= +5.0 V
Rating
7
−8
0 to V
EE
±
0.5
−40 to +85
−65 to +150
190
130
41 to 44
185
140
41 to 44
±
5%
129
84
265
35 to 40
Unit
V
V
V
mA
°C
°C
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C
°C/W
Thermal Resistance (Junction−to−Case)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)
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2
MC10ELT25, MC100ELT25
Table 4. 10ELT SERIES NECL INPUT DC CHARACTERISTICS
V
CC
= 5.0 V; V
EE
= −5.0 V; GND = 0 V (Note 3)
−40°C
Symbol
V
IH
V
IL
V
BB
V
IHCMR
I
IH
I
IL
Characteristic
Input HIGH Voltage (Single−Ended) (Note 4)
Input LOW Voltage (Single−Ended) (Note 4)
Output Voltage Reference
Input HIGH Voltage Common Mode Range
(Differential) (Notes 4 and 5)
Input HIGH Current
Input LOW Current
0.5
Min
−1230
−1950
−1.43
−2.8
Typ
Max
−890
−1500
−1.30
0.0
255
0.5
Min
−1130
−1950
−1.35
−2.8
25°C
Typ
Max
−810
−1480
−1.25
0.0
175
0.3
Min
−1060
−1950
−1.31
−2.8
85°C
Typ
Max
−720
−1445
−1.19
0.0
175
Unit
mV
mV
V
V
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
3. Input parameters vary 1:1 with GND. V
EE
can vary +0.06 V to −0.5 V.
4. TTL output R
L
= 500
W
to GND
5. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with GND.
Table 5. 100ELT SERIES NECL INPUT DC CHARACTERISTICS
V
CC
= 5.0 V; V
EE
= −5.0 V; GND = 0 V (Note 6)
−40°C
Symbol
V
IH
V
IL
V
BB
V
IHCMR
I
IH
I
IL
Characteristic
Input HIGH Voltage (Single−Ended) (Note 7)
Input LOW Voltage (Single−Ended) (Note 7)
Output Voltage Reference
Input HIGH Voltage Common Mode Range
(Differential) (Notes 7 and 8)
Input HIGH Current
Input LOW Current
0.5
Min
−1165
−1810
−1.38
−2.8
Typ
Max
−880
−1475
−1.26
0.0
255
0.5
Min
−1165
−1810
−1.38
−2.8
25°C
Typ
Max
−880
−1475
−1.26
0.0
175
0.5
Min
−1165
−1810
−1.38
−2.8
85°C
Typ
Max
−880
−1475
−1.26
0.0
175
Unit
mV
mV
V
V
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
6. Input parameters vary 1:1 with GND. V
EE
can vary +0.8 V to −0.5 V.
7. TTL output R
L
= 500
W
to GND
8. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with GND.
Table 6. TTL OUTPUT DC CHARACTERISTICS
V
CC
= 4.5 V to 5.5 V; T
A
= −40°C to +85°C
Symbol
V
OH
V
OL
I
CCH
I
CCL
I
EE
I
OS
Characteristic
Output HIGH Voltage
Output LOW Voltage
Power Supply Current
Power Supply Current
Negative Power Supply Current
Output Short Circuit Current
−150
Condition
I
OH
= −3.0 mA
I
OL
= 24 mA
11
13
15
Min
2.4
0.5
16
18
21
−60
Typ
Max
Unit
V
V
mA
mA
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
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3
MC10ELT25, MC100ELT25
Table 7. AC CHARACTERISTICS
V
CC
= 5.0 V; V
EE
= −5.0 V; GND= 0 V (Note 9 and Note 10)
−40°C
Symbol
f
max
t
PLH
t
PHL
t
JITTER
t
r
t
f
V
PP
Characteristic
Maximum Toggle Frequency
Propagation Delay @ 1.5 V
Propagation Delay @ 1.5 V
Random Clock Jitter (RMS)
Output Rise/Fall Times QTTL
10% − 90%
Input Swing (Note 11)
200
1000
200
1.7
2.6
3.6
4.1
1.7
2.6
35
1.9
2.3
1000
200
1000
Min
Typ
Max
Min
25°C
Typ
100
3.6
4.1
1.7
2.6
3.6
4.1
Max
Min
85°C
Typ
Max
Unit
MHz
ns
ns
ps
ns
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
9. V
CC
can vary
±
0.25 V.
V
EE
can vary +0.06 V to −0.5 V for 10ELT; V
EE
can vary +0.8 V to −0.5 V for 100ELT.
10. R
L
= 500
W
to GND and C
L
= 20 pF to GND. Refer to Figure 2.
11. V
PP
(min) is the minimum input swing for which AC parameters are guaranteed. The device has a DC gain of
≈
40.
APPLICATION
TTL RECEIVER
CHARACTERISTIC TEST
*C
L
includes
fixture
capacitance
C
L
*
R
L
AC TEST LOAD
GND
Figure 2. TTL Output Loading Used for Device Evaluation
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MC10ELT25, MC100ELT25
ORDERING INFORMATION
Device
MC10ELT25DG
MC10ELT25DR2G
MC10ELT25DTG
MC10ELT25DTR2G
MC10ELT25MNR4G
MC100ELT25DG
MC100ELT25DR2G
MC100ELT25DTG
MC100ELT25DTR2G
MC100ELT25MNR4G
Package
SOIC−8
(Pb−Free)
SOIC−8
(Pb−Free)
TSSOP−8
(Pb−Free)
TSSOP−8
(Pb−Free)
DFN8
(Pb−Free)
SOIC−8
(Pb−Free)
SOIC−8
(Pb−Free)
TSSOP−8
(Pb−Free)
TSSOP−8
(Pb−Free)
DFN8
(Pb−Free)
Shipping
†
98 Units / Rail
2500 / Tape & Reel
100 Units / Rail
2500 / Tape & Reel
1000 / Tape & Reel
98 Units / Rail
2500 / Tape & Reel
100 Units / Rail
2500 / Tape & Reel
1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
− ECL Clock Distribution Techniques
− Designing with PECL (ECL at +5.0 V)
− ECLinPSt I/O SPiCE Modeling Kit
− Metastability and the ECLinPS Family
− Interfacing Between LVDS and ECL
− The ECL Translator Guide
− Odd Number Counters Design
− Marking and Date Codes
− Termination of ECL Logic Devices
− Interfacing with ECLinPS
− AC Characteristics of ECL Devices
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