Datasheet
Serial EEPROM Series
Standard EEPROM
Plug & Play EEPROM
BU9883FV-W
●General
Description
BU9883FV-W is for DDC 3 ports, 2K x 8 bit array 3 BANK EEPROM.
●Features
■
There are 3 BANKs, 1 BANK compose of 256 word address x 8 bit
EEPROM
■
There are 3 DDC interface channels, and each channel can access
each BANK independently from other ports.
■
2K bit X 3 BANK memory bits can be accessed from write port (Port0).
■
Operate voltage (3.0V to 5.5V)
■
Built in diode for power supply from HDMI ports and system.
■
Automatic erase
■
8 byte page write mode
■
Low power consumption
At write action ( 5.0V )
: 1.2mA (Typ.)
At read action (5.0V)
: 0.2mA(Typ.) 1port action
At Standby action ( 5.0V ) : 50μA(Typ.)
■
DATA security
■
Write Protect pin can switch write port
■
Inhibit to WRITE at low V
CC
■
Endurance
: 1,000,000 erase/write cycles
■
Data retention
40 years
■
Filtered inputs in all SCL・SDA for noise suppression
■
Shipment data all address FFh
●Typical
Application Circuit
HDMI Sink
0.1uF
PWR_HDMI1
DDC_SCL1
DDC_SDA1
0.1uF
PWR_HDMI2
DDC_SCL2
DDC_SDA2
0.1uF
SCL0
PWR_HDMI3
DDC_SCL3
DDC_SDA3
47KΩ
47KΩ
47KΩ
47KΩ
47KΩ
47KΩ
●Package
W(Typ.) x D(Typ.) x H(Max.)
SSOP-B16
5.00mm x 6.40mm x 1.35mm
Vcc1
SCL1
SDA1
PWR_SYS
Vcc0
0.1uF
WPB
μ
Controller
WPB_OUT
I
2
C_SCL
0.1uF
I
2
C_SDA
ROHM
Vcc OUT
Vcc2
BU9883FV-W
SCL2
SDA2
Vcc3
SDA0
SCL3
SDA3
GND
HDMI
Receiver
SDA3
SCL3
SDA2
SCL2
SDA1
SCL1
SCL_SINK
DDC_SCL
HDMI
Switch
SDA_SINK
DDC_SDA
○Product
structure：Silicon monolithic integrated circuit
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・14・001
○This
product is not designed protection against radioactive rays
1/26
TSZ02201-0R2R0G100420-1-2
17.Aug.2015 Rev.002
BU9883FV-W
●Absolute
Maximum Ratings
(Ta=25℃)
Parameter
Symbol
Rating
Supply Voltage
V
CC
-0.3 to 6.5
Power Dissipation
Pd
0.4
Storage Temperature
Tstg
-65 to 125
Operating Temperature
Topr
-40 to 85
Terminal Voltage
-
-0.3 to V
CC
＋0.3
Unit
V
W
℃
℃
V
Remarks
Degradation is done at 3.0mW/℃ for operation above 25℃
The Max value of terminal voltage is not over 6.5V
●Memory
cell characteristics
(Ta=25℃, V
CC
0 to 3 = 3.0V to 5.5V)
Specification
Parameter
Min.
Typ.
*1
Write/Erase Cycle
1,000,000
-
*1
Data Retention
40
-
*1:Not 100％ TESTED
Max.
-
-
Unit
Cycles
Years
●Recommended
Operating Ratings
Parameter
Supply Voltage
Input Voltage
Symbol
V
CC
VIN
Rating
3.0 to 5.5
0 to V
CC
0 to 3
Unit
V
●Input/output
capacity
(Ta=25℃, Frequency=5MHz)
Parameter
Symbol
SDA pins (SDA0,1,2,3)
*1
SCL pins (SCL0,1,2,3)
*1
*1:Not 100％ TESTED
Min.
-
-
Typ.
7
7
Max.
-
-
Unit
pF
pF
C
IN
C
IN2
●Electrical
characteristics -DC operating
(Unless otherwise specified, Ta=-40℃
Specification
Parameter
Symbol
Unit
Min.
Typ.
Max.
"H" Input Voltage0
VIH0
0.7xV
CC
0
-
V
CC
0+0.5
V
"L" Input Voltage0
VIL0
-0.3
-
0.3xV
CC
0
V
"H" Input Voltage1
VIH1
0.7xV
CC
1
-
V
CC
1+0.5
V
"L" Input Voltage1
VIL1
-0.3
-
0.3xV
CC
1
V
"H" Input Voltage2
VIH2
0.7xV
CC
2
-
V
CC
2+0.5
V
"L" Input Voltage2
VIL2
-0.3
-
0.3xV
CC
2
V
"H" Input Voltage3
VIH3
0.7xV
CC
3
-
V
CC
3+0.5
V
"H" Input Voltage3
VIL3
-0.3
-
0.3xV
CC
3
V
"L" Output Voltage0
VOL0
-
-
0.4
V
"L" Output Voltage1
VOL1
-
-
0.4
V
"L" Output Voltage2
VOL2
-
-
0.4
V
"L" Output Voltage3
VOL3
-
-
0.4
V
WP "H" Input Voltage
VIH4
0.7xV
CC
0
-
V
CC
0+0.3
V
WP "L" Input Voltage
VIL4
-0.3
-
0.3xV
CC
V
Input Leakage Current0
ILI0
-1
-
1
μA
Input Leakage Current1
ILI1
55
110
230
μA
Output Leakage Current0
ILO0
-1
-
1
μA
ICC1
Operating Current
ICC2
Standby Current
Standby Current
Standby Current
Standby Current
ISB0
ISB1
ISB2
ISB3
-
-
-
-
-
-
-
-
-
-
1.0
100
100
100
100
mA
μA
μA
μA
μA
-
-
2.0
mA
to 85℃, V
CC
0 to 3 = 3.0V to 5.5V)
Test condition
3.0≦V
CC
0≦5.5V(SCL0, SDA0)
3.0≦V
CC
0≦5.5V(SCL0, SDA0)
3.0≦V
CC
1≦5.5V(SCL1, SDA1)
3.0≦V
CC
1≦5.5V(SCL1, SDA1)
3.0≦V
CC
2≦5.5V(SCL2, SDA2)
3.0≦V
CC
2≦5.5V(SCL2, SDA2)
3.0≦V
CC
3≦5.5V(SCL3, SDA3)
3.0≦V
CC
3≦5.5V(SCL3, SDA3)
IOL=3.0mA , 3.0V≦V
CC
0≦5.5V(SDA0)
IOL=3.0mA , 3.0V≦V
CC
1≦5.5V(SDA1)
IOL=3.0mA , 3.0V≦V
CC
2≦5.5V(SDA2)
IOL=3.0mA , 3.0V≦V
CC
3≦5.5V(SDA3)
3.0≦V
CC
0≦5.5V(WPB)
3.0≦V
CC
0≦5.5V(WPB)
VIN=0 to 5.5V(SCL0 to 3)
WPB=5.5V , V
CC
=5.5V
VOUT=0 to 5.5(SDA0 to 3)
V
CC
0=5.5V, fSCL=400kHz，tWR=5ms
Byte Write, Page Write
V
CC
0 to 3=5.5V, fSCL=400kHz
Random Read, Current Read,Sequential
Read, (each port operation)
V
CC
0=5.5V, SDA0 to 3=SCL0 to 3=5.5V,
WPB=GND
V
CC
1=5.5V, SDA0 to 3=SCL0 to 3=5.5V,
WPB=GND
V
CC
2=5.5V, SDA0 to 3=SCL0 to 3=5.5V,
WPB=GND
V
CC
3=5.5V, SDA0 to 3=SCL0 to 3=5.5V,
WPB=GND
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
2/26
TSZ02201-0R2R0G100420-1-2
17.Aug.2015 Rev.002
BU9883FV-W
●Electrical
characteristics -AC Operating
(Ta=-40℃ to 85℃, V
CC
0 to 3 = 3.0V to 5.5V)
3.0≦V
CC
0 to 3≦5.5V
Parameter
Symbol
Min.
Typ.
Max.
Clock Frequency
Data Clock High Period
Data Clock Low Period
SDA0 to 3 and SCL0 to 3 Rise Time
*1
SDA0 to 3 and SCL0 to 3 Fall Time
*1
Start Condition Hold Time
Start Condition Setup Time
Input Data Hold Time
Input Data Setup Time
Output Data Delay Time
Output Data Hold Time
Stop Condition Setup Time
Bus Free Time
Write Cycle Time
Noise Spike Width (SDA0 to 3 and SCL0 to 3)
WP Hold Time
WP Setup Time
WP valid time
*1 : Not 100% TESETED
Unit
kHz
μs
μs
μs
μs
μs
μs
ns
ns
μs
μs
μs
μs
ms
μs
ns
μs
μs
f
SCL
t
HIGH
t
LOW
t
R
t
F
t
HD:STA
t
SU:STA
t
HD
:
DAT
t
SU:DAT
t
PD
t
DH
t
SU:STO
t
BUF
t
WR
tI
t
HD:WP
t
SU:WP
t
HIGH:WP
-
0.6
1.2
-
-
0.6
0.6
0
100
0.1
0.1
0.6
1.2
-
-
0
0.1
1.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
400
-
-
0.3
0.3
-
-
-
-
0.9
-
-
-
5
0.1
-
-
-
●Sync
Data Input / Output Timing
t
R
SCL
t
HD
:STA
SDA
(IN)
t
BUF
SDA
(OUT)
t
PD
t
DH
SDA
t
F
t
HIGH
t
SU
:DAT
t
LOW
t
HD
:DAT
SCL
t
SU
:STA
t
HD
:STA
t
SU
:STO
START BIT
STOP BIT
Figure 1. SYNCHRONOUS DATA TIMING
○SDA
data is latched into the chip at the rising edge of the SCL clock. (This is commonness in all port.)
○Output
date toggles at the falling edge of the SCL clock. (This is commonness in all port.)
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
3/26
TSZ02201-0R2R0G100420-1-2
17.Aug.2015 Rev.002
BU9883FV-W
●Block
Diagram
Vcc1
Vcc2
Vcc3
Voltage
Detect
Logic
Vcc0
LDO
Low Voltage
Logic
V
CC
OUT
WPB
Port 1
SCL1
SDA1
EN I/O
(PORT1)
LEVEL
Shifter
CONTROL
RD
BANK0
(2Kbit EEPROM)
WR
RD
Port 0
Port 2
SCL2
SDA2
EN
I/O
(PORT2)
LEVEL
Shifter
RD
CONTROL
BANK1
(2Kbit EEPROM)
WR
CON
TROL
LEVEL
Shifter
EN
I/O
(PORT0) SCL0
SDA0
SCL0
SDA0
RD
Port 3
SCL3
SDA3
EN
I/O
(PORT3)
LEVEL
Shifter
CONTROL
RD
BANK2
(2Kbit EEPROM)
WR
RD
●Pin
Configuration
Vcc1
SCL1
SDA1
WPB
1
2
3
4
5
6
7
8
TOP VIEW
16
15
14
13
12
11
10
9
Vcc2
SCL2
SDA2
N.C
GND
SDA3
SCL3
Vcc3
BU9883FV-W
V
CC
OUT
SDA0
SCL0
Vcc0
●Pin
Descriptions
PIN No.
PIN NAME
1
V
CC
1
2
SCL1
3
SDA1
4
WPB
5
V
CC
OUT
6
SDA0
7
SCL0
8
V
CC
0
9
V
CC
3
10
SCL3
11
SDA3
12
GND
13
N.C
14
SDA2
15
SCL2
16
V
CC
2
I/O
-
Input
Input /output
Input
-
Input /output
Input
-
-
Input
Input /output
-
-
Input /output
Input
-
FUNCTIONS
Power Supply
Serial clock input
Slave and word address, Serial data input serial data output
Write protect terminal(1 : Write enable, 0 : Write disable)
Terminal of diode. Connect Bypass capacitor.
Slave and word address, Serial data input serial data output
Serial clock input
Power Supply
Power Supply
Serial clock input
Slave and word address, Serial data input serial data output
Reference voltage of all input / output
None connect terminal.
Don’t connect each other.
Slave and word address, Serial data input serial data output
Serial clock input
Power Supply
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© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
4/26
TSZ02201-0R2R0G100420-1-2
17.Aug.2015 Rev.002
BU9883FV-W
●Typical
Performance Curves
(The following values are Typ. ones.)
Figure 2. ‘H’ Input Voltage0 V
IH0
(SCL0,SDA0)
Figure 3. ‘H’ Input Voltage1 V
IH1
(SCL1,SDA1)
Figure 4. ‘H’ Input Voltage2 V
IH2
(SCL2,SDA2)
Figure 5. ‘H’ Input Voltage3 V
IH3
(SCL3,SDA3)
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
5/26
TSZ02201-0R2R0G100420-1-2
17.Aug.2015 Rev.002
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