CMOS SyncFIFO™
64 x 8, 256 x 8,
512 x 8, 1,024 x 8,
2,048 x 8 and 4,096 x 8
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
IDT72420
IDT72200
IDT72210
IDT72220
IDT72230
IDT72240
DESCRIPTION:
The IDT72420/72200/72210/72220/72230/72240 SyncFIFO™ are very
high-speed, low-power First-In, First-Out (FIFO) memories with clocked
read and write controls. These devices have a 64, 256, 512, 1,024, 2,048,
and 4,096 x 8-bit memory array, respectively. These FIFOs are applicable
for a wide variety of data buffering needs, such as graphics, Local Area
Networks (LANs), and interprocessor communication.
These FIFOs have 8-bit input and output ports. The input port is
controlled by a free-running clock (WCLK), and a Write Enable pin (WEN).
Data is written into the Synchronous FIFO on every clock when
WEN
is
asserted. The output port is controlled by another clock pin (RCLK) and a
Read Enable pin (REN). The Read Clock can be tied to the Write Clock for
single clock operation or the two clocks can run asynchronous of one
another for dual clock operation. An Output Enable pin (OE) is provided on
the read port for three-state control of the output.
These Synchronous FIFOs have two endpoint flags, Empty (EF) and Full
(FF). Two partial flags, Almost-Empty (AE) and Almost-Full (AF), are
provided for improved system control. The partial (AE) flags are set to
Empty+7 and Full-7 for
AE
and
AF
respectively.
These FIFOs are fabricated using IDT’s high-speed submicron CMOS
technology.
64 x 8-bit organization (IDT72420)
256 x 8-bit organization (IDT72200)
512 x 8-bit organization (IDT72210)
1,024 x 8-bit organization (IDT72220)
2,048 x 8-bit organization (IDT72230)
4,096 x 8-bit organization (IDT72240)
10 ns read/write cycle time (IDT72420/72200/72210/72220/72230/
72240)
Read and Write Clocks can be asynchronous or coincidental
Dual-Ported zero fall-through time architecture
Empty and Full flags signal FIFO status
Almost-Empty and Almost-Full flags set to Empty+7 and Full-7,
respectively
Output enable puts output data bus in high-impedance state
Produced with advanced submicron CMOS technology
Available in 28-pin 300 mil plastic DIP
For surface mount product please see the IDT72421/72201/72211/
72221/72231/72241 data sheet
Industrial temperature range (–40°C to +85°C) is available
°
°
Green parts available, see ordering information
FUNCTIONAL BLOCK DIAGRAM
D0 - D7
WCLK
WEN
INPUT REGISTER
FLAG
LOGIC
RAM ARRAY
64 x 8, 256 x 8,
512 x 8, 1,024 x 8,
2,048 x 8, 4,096 x 8
EF
AE
AF
FF
WRITE CONTROL
LOGIC
WRITE POINTER
READ POINTER
READ CONTROL
LOGIC
OUTPUT REGISTER
RESET LOGIC
RCLK
RS
OE
Q0 - Q7
REN
2680 drw01
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. The SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
FEBRUARY 2006
DSC-2680/4
©2006
Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
1
IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™
64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
D4
D3
D2
D1
D0
AF
AE
GND
RCLK
REN
OE
EF
FF
Q0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
D5
D6
D7
RS
WEN
WCLK
VCC
Q7
Q6
Q5
Q4
Q3
Q2
Q1
2680 drw02
PLASTIC THIN DIP (P28-2, order code: TP)
TOP VIEW
PIN DESCRIPTIONS
Symbol
D
0
- D
7
RS
WCLK
WEN
Q
0
- Q
7
RCLK
REN
OE
EF
AE
AF
FF
V
CC
GND
Name
Data Inputs
Reset
Write Clock
Write Enable
Data Outputs
Read Clock
Read Enable
Output Enable
Empty Flag
Almost-Empty Flag
Almost-Full Flag
Full Flag
Power
Ground
I/O
I
I
I
I
O
I
I
I
O
O
O
O
Description
Data inputs for a 8-bit bus.
When
RS
is set LOW, internal read and write pointers are set to the first location of the RAM array,
FF
and
AF
go
HIGH, and
AE
and
EF
go LOW. A reset is required before an initial WRITE after power-up.
Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when
WEN
is asserted.
When
WEN
is LOW, data is written into the FIFO on every LOW-to-HIGH transition of WCLK. Data will not be written
into the FIFO if the
FF
is LOW.
Data outputs for a 8-bit bus.
Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when
REN
is asserted.
When
REN
is LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. Data will not be read from
the FIFO if the
EF
is LOW.
When
OE
is LOW, the data output bus is active. If
OE
is HIGH, the output data bus will be in a high-impedance
state.
When
EF
is LOW, the FIFO is empty and further data reads from the output are inhibited. When
EF
is HIGH, the FIFO
is not empty.
EF
is synchronized to RCLK.
When
AE
is LOW, the FIFO is almost empty based on the offset Empty+7.
AE
is synchronized to RCLK.
When
AF
is LOW, the FIFO is almost full based on the offset Full-7.
AF
is synchronized to WCLK.
When
FF
is LOW, the FIFO is full and further data writes into the input are inhibited. When
FF
is HIGH, the FIFO is not
full.
FF
is synchronized to WCLK.
One +5 volt power supply pin.
One 0 volt ground pin.
2
FEBRUARY 10, 2006
IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™
64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
T
STG
I
OUT
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Rating
Terminal Voltage with
Respect to GND
Storage Temperature
DC Output Current
Com'l & Ind'l
–0.5 to +7.0
–55 to +125
–50 to +50
Unit
V
°C
mA
RECOMMENDED OPERATING
CONDITIONS
Symbol
V
CC
GND
V
IH
V
IL
T
A
Parameter
Supply Voltage
Commercial
Supply Voltage
Input High Voltage
Commercial
Input Low Voltage
Commercial
Operating Temperature
Commercial
Min.
4.5
0
2.0
—
0
Typ. Max.
5.0
5.5
0
—
—
—
0
—
0.8
70
Unit
V
V
V
V
°C
DC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 5V ± 10%, T
A
= 0°C to +70°C)
IDT72420
IDT72200
IDT72210
IDT72220
IDT72230
IDT72240
Commercial
t
CLK
= 10, 15, 25 ns
Typ.
—
—
—
—
—
—
Symbol
I
LI
(1)
I
LO
(2)
V
OH
V
OL
I
CC1
(3,4,5)
I
CC2
(3,6)
Parameter
Input Leakage Current (any input)
Output Leakage Current
Output Logic “1” Voltage, I
OH
= –2 mA
Output Logic “0” Voltage, I
OL
= 8 mA
Active Power Supply Current
Standby Current
Min.
–1
–10
2.4
—
—
—
Max.
1
10
—
0.4
40
5
NOTES:
1. Measurements with 0.4
≤
V
IN
≤
V
CC
.
2.
OE
≥
V
IH,
0.4
≤
V
OUT
≤
V
CC
.
3. Tested with outputs open (I
OUT
= 0).
4. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
5. Typical I
CC1
= 1.7 + 0.7*f
S
+ 0.02*C
L
*f
S
(in mA).
These equations are valid under the following conditions:
V
CC
= 5V, T
A
= 25
°
C, f
S
= WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at f
S
/2, C
L
= capacitive load (in pF).
6. All Inputs = V
CC
- 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
3
FEBRUARY 10, 2006
IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™
64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 5V ± 10%, T
A
= 0°C to + 70°C)
IDT72420L10
IDT72200L10
IDT72210L10
IDT72220L10
IDT72230L10
IDT72240L10
Min.
Max.
—
100
2
10
4.5
4.5
3
0.5
3
0.5
10
8
8
—
0
2
2
—
—
—
—
4
10
6.5
—
—
—
—
—
—
—
—
—
—
10
—
6
6
6.5
6.5
6.5
6.5
—
—
Commercial
IDT72420L15
IDT72200L15
IDT72210L15
IDT72220L15
IDT72230L15
IDT72240L15
Min.
Max.
—
66.7
2
15
6
6
4
1
4
1
15
10
10
—
0
3
3
—
—
—
—
6
15
10
—
—
—
—
—
—
—
—
—
—
15
—
8
8
10
10
10
10
—
—
IDT72420L25
IDT72200L25
IDT72210L25
IDT72220L25
IDT72230L25
IDT72240L25
Min.
Max.
—
40
2
25
10
10
6
1
6
1
15
15
15
—
0
3
3
—
—
—
—
10
18
15
—
—
—
—
—
—
—
—
—
—
25
—
13
13
15
15
15
15
—
—
Symbol
Parameter
Clock Cycle Frequency
f
S
t
A
t
CLK
t
CLKH
t
CLKL
t
DS
t
DH
t
ENS
t
ENH
t
RS
t
RSS
t
RSR
t
RSF
t
OLZ
t
OE
t
OHZ
t
WFF
t
REF
t
AF
t
AE
t
SKEW1
t
SKEW2
Data Access Time
Clock Cycle Time
Clock High Time
Clock Low Time
Data Setup Time
Data Hold Time
Enable Setup Time
Enable Hold Time
Reset Pulse Width
(1)
Reset Setup Time
Reset Recovery Time
Reset to Flag and Output Time
Output Enable to Output in Low-Z
(2)
Output Enable to Output Valid
Output Enable to Output in High-Z
(2)
Write Clock to Full Flag
Read Clock to Empty Flag
Write Clock to Almost-Full Flag
Read Clock to Almost-Empty Flag
Skew time between Read Clock & Write Clock for
Empty Flag & Full Flag
Skew time between Read Clock & Write Clock for
Almost-Empty Flag & Almost-Full Flag
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Pulse widths less than minimum values are not allowed.
2. Values guaranteed by design, not currently tested.
CAPACITANCE
(T
A
= +25°C, f = 1.0 MHz)
Symbol
C
IN
(2)
(1, 2)
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
10
10
Unit
pF
pF
D.U.T.
680Ω
5V
1.1KΩ
C
OUT
NOTES:
1. With output deselected. (OE
≥
VIH)
2. Characterized values, not currently tested.
30pF*
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figure 1
4
2680 drw03
or equivalent circuit
Figure 1. Output Load
*Includes jig and scope capacitances.
FEBRUARY 10, 2006
IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™
64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8
COMMERCIAL TEMPERATURE RANGE
SIGNAL DESCRIPTIONS
INPUTS:
Data In (D
0
–D
7
)
— Data inputs for 8-bit wide data.
CONTROLS:
RESET (RS) —
Reset is accomplished whenever the Reset (RS) input is
taken to a LOW state. During reset, both internal read and write pointers are
set to the first location. A reset is required after power up before a write
operation can take place. The Full Flag (FF) and Almost-Full Flag (AF) will
be reset to HIGH after t
RSF
. The Empty Flag (EF) and Almost-Empty Flag
(AE) will be reset to LOW after t
RSF
. During reset, the output register is
initialized to all zeros.
WRITE CLOCK (WCLK) —
A write cycle is initiated on the LOW-to-HIGH
transition of the Write Clock (WCLK). Data setup and hold times must be met
in respect to the LOW-to-HIGH transition of the Write Clock. The Full Flag
(FF) and Almost-Full Flag (AF) are synchronized with respect to the LOW-
to-HIGH transition of the Write Clock.
The Write and Read Clocks can be asynchronous or coincident.
WRITE ENABLE (WEN) —
When Write Enable (WEN) is LOW, data can
be loaded into the input register and RAM array on the LOW-to-HIGH
transition of every Write Clock (WCLK). Data is stored in the RAM array
sequentially and independently of any on-going read operation.
When Write Enable (WEN) is HIGH, the input register holds the previous
data and no new data is allowed to be loaded into the register.
To prevent data overflow, the Full Flag (FF) will go LOW, inhibiting
further write operations. Upon the completion of a valid read cycle, the Full
Flag (FF) will go HIGH after t
WFF
, allowing a valid write to begin. Write
Enable (WEN) is ignored when the FIFO is full.
READ CLOCK (RCLK) —
Data can be read on the outputs on the LOW-to-
HIGH transition of the Read Clock (RCLK). The Empty Flag (EF) and
Almost-Empty flag (AE) are synchronized with respect to the LOW-to-HIGH
transition of the Read Clock.
The Write and Read Clocks can be asynchronous or coincident.
READ ENABLE (REN) —
When Read Enable (REN) is LOW, data is read
from the RAM array to the output register on the LOW-to-HIGH transition of
the Read Clock (RCLK).
When Read Enable (REN) is HIGH, the output register holds the
previous data and no new data is allowed to be loaded into the register.
When all the data has been read from the FIFO, the Empty Flag (EF) will
go LOW, inhibiting further read operations. Once a valid write operation has
been accomplished, the Empty Flag (EF) will go HIGH after t
REF
and a valid
read can begin. Read Enable (REN) is ignored when the FIFO is empty.
OUTPUT ENABLE (OE) —
When Output Enable (OE) is enabled (LOW),
the parallel output buffers receive data from the output register. When
Output Enable (OE) is disabled (HIGH), the Q output data bus is in a high-
impedance state.
OUTPUTS:
FULL FLAG (FF) —
The Full Flag (FF) will go LOW, inhibiting further write
operation, when the device is full. If no reads are performed after Reset
(RS), the Full Flag (FF) will go LOW after 64 writes for the IDT72420, 256
writes for the IDT72200, 512 writes for the IDT72210, 1,024 writes for the
IDT72220, 2,048 writes for the IDT72230, and 4,096 writes for the IDT72240.
The Full Flag (FF) is synchronized with respect to the LOW-to-HIGH
transition of the Write Clock (WCLK).
EMPTY FLAG (EF) —
The Empty Flag (EF) will go LOW, inhibiting further
read operations, when the read pointer is equal to the write pointer,
indicating the device is empty.
The Empty Flag (EF) is synchronized with respect to the LOW-to-HIGH
transition of the Read Clock (RCLK).
ALMOST-FULL FLAG (AF) —
The Almost-Full Flag (AF) will go LOW when
the FIFO reaches the almost-full condition. If no reads are performed after
Reset (RS), the Almost-Full Flag (AF) will go LOW after 57 writes for the
IDT72420, 249 writes for the IDT72200, 505 writes for the IDT72210, 1,017
writes for the IDT72220, 2,041 writes for the IDT72230 and 4,089 writes for
the IDT72240.
The Almost-Full Flag (AF) is synchronized with respect to the LOW-to-
HIGH transition of the Write Clock (WCLK).
ALMOST-EMPTY FLAG (AE) —
The Almost-Empty Flag (AE) will go LOW
when the FIFO reaches the almost-empty condition. If no reads are
performed after Reset (RS), the Almost-Empty Flag (AE) will go HIGH after
8 writes for the IDT72420, IDT72200, IDT72210, IDT72220, IDT72230 and
IDT72240.
The Almost-Empty Flag (AE) is synchronized with respect to the LOW-
to-HIGH transition of the Read Clock (RCLK).
DATA OUTPUTS (Q
0
–Q
7
) —
Data outputs for 8-bit wide data.
TABLE 1 — STATUS FLAGS
IDT72420
0
1 to 7
8 to 56
57 to 63
64
IDT72200
0
1 to 7
8 to 248
249 to 255
256
Number of Words in FIFO
IDT72210
IDT72220
0
1 to 7
8 to 504
505 to 511
512
0
1 to 7
8 to 1,016
1,017 to 1,023
1,024
IDT72230
0
1 to 7
8 to 2,040
2,041 to 2,047
2,048
IDT72240
0
1 to 7
8 to 4,088
4,089 to 4,095
4,096
FF
H
H
H
H
L
AF
H
H
H
L
L
AE
L
L
H
H
H
EF
L
H
H
H
H
5
FEBRUARY 10, 2006
FPGA/CPLD
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