74AC299, 74ACT299 — 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins
January 2008
74AC299, 74ACT299
8-Input Universal Shift/Storage Register with Common
Parallel I/O Pins
Features
■
I
CC
and I
OZ
reduced by 50%
■
Common parallel I/O for reduced pin count
■
Additional serial inputs and outputs for expansion
■
Four operating modes: shift left, shift right, load
General Description
The AC/ACT299 is an 8-bit universal shift/storage regis-
ter with 3-STATE outputs. Four modes of operation are
possible: hold (store), shift left, shift right and load data.
The parallel load inputs and flip-flop outputs are multi-
plexed to reduce the total number of package pins. Addi-
tional outputs are provided for flip-flops Q
0
, Q
7
to allow
easy serial cascading. A separate active LOW Master
Reset is used to reset the register.
and store
■
3-STATE outputs for bus-oriented applications
■
Outputs source/sink 24mA
■
ACT299 has TTL-compatible inputs
Ordering Information
Order Number
74AC299SC
74AC299SJ
74AC299MTC
74AC299PC
74ACT299SC
74ACT299MTC
74ACT299PC
Package
Number
M20B
M20D
MTC20
N20A
M20B
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1988 Fairchild Semiconductor Corporation
74AC299, 74ACT299 Rev. 1.4.0
www.fairchildsemi.com
74AC299, 74ACT299 — 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins
Connection Diagram
Logic Symbols
IEEE/IEC
Pin Description
Pin Names
CP
DS
0
DS
7
S
0
, S
1
MR
OE
1
, OE
2
I/O
0
–I/O
7
Q
0
, Q
7
Description
Clock Pulse Input
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Mode Select Inputs
Asynchronous Master Reset
3-STATE Output Enable Inputs
Parallel Data Inputs or 3-STATE
Parallel Outputs
Serial Outputs
Functional Description
The AC/ACT299 contains eight edge-triggered D-type
flip-flops and the interstage logic necessary to perform
synchronous shift left, shift right, parallel load and hold
operations. The type of operation is determined by S
0
and S
1
, as shown in the Truth Table. All flip-flop outputs
are brought out through 3-STATE buffers to separate I/O
pins that also serve as data inputs in the parallel load
mode. Q
0
and Q
7
are also brought out on other pins for
expansion in serial shifting of longer words.
A LOW signal on MR overrides the Select and CP inputs
and resets the flip-flops. All other state changes are initi-
ated by the rising edge of the clock. Inputs can change
when the clock is in either state provided only that the
recommended setup and hold times, relative to the rising
edge of CP, are observed.
A HIGH signal on either OE
1
or OE
2
disables the
3-STATE buffers and puts the I/O pins in the high imped-
ance state. In this condition the shift, hold, load and reset
operations can still occur. The 3-STATE buffers are also
disabled by HIGH signals on both S
0
and S
1
in prepara-
tion for a parallel load operation.
Truth Table
Inputs
MR S
1
L
H
H
H
H
X
H
L
H
L
Response
CP
X
Asynchronous Reset;
Q
0
–Q
7
=
LOW
Parallel Load; I/O
n
→
Q
n
Shift Right;
DS
0
→
Q
0
, Q
0
→
Q
1
, etc.
Shift Left,
DS
7
→
Q
7
, Q
7
→
Q
6
, etc.
X
Hold
S
0
X
H
H
L
L
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
=
LOW-to-HIGH Transition
©1988 Fairchild Semiconductor Corporation
74AC299, 74ACT299 Rev. 1.4.0
www.fairchildsemi.com
2
74AC299, 74ACT299 — 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
©1988 Fairchild Semiconductor Corporation
74AC299, 74ACT299 Rev. 1.4.0
www.fairchildsemi.com
3
74AC299, 74ACT299 — 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
I
IK
Supply Voltage
DC Input Diode Current
V
I
= −
0.5V
V
I
=
V
CC
+
0.5
V
I
I
OK
DC Input Voltage
DC Output Diode Current
V
O
= −
0.5V
V
O
=
V
CC
+
0.5V
V
O
I
O
DC Output Voltage
Parameter
Rating
−
0.5V to
+
7.0V
−
20mA
+
20mA
−
0.5V to V
CC
+
0.5V
−
20mA
+
20mA
−
0.5V to V
CC
+
0.5V
±
50mA
±
50mA
−
65
°
C to
+
150
°
C
140
°
C
DC Output Source or Sink Current
I
CC
or I
GND
DC V
CC
or Ground Current per Output Pin
T
STG
Storage Temperature
T
J
Junction Temperature
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
AC
ACT
V
I
V
O
T
A
∆
V /
∆
t
∆V
/
∆t
Input Voltage
Output Voltage
Operating Temperature
Parameter
Supply Voltage (unless otherwise specified)
Rating
2.0V to 6.0V
4.5V to 5.5V
0V to V
CC
0V to V
CC
−
40
°
C to
+
85
°
C
125mV/ns
125mV/ns
Minimum Input Edge Rate, AC Devices:
V
IN
from 30% to 70% of V
CC
, V
CC
@ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate, ACT Devices:
V
IN
from 0.8V to 2.0V, V
CC
@ 4.5V, 5.5V
©1988 Fairchild Semiconductor Corporation
74AC299, 74ACT299 Rev. 1.4.0
www.fairchildsemi.com
4
74AC299, 74ACT299 — 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins
DC Electrical Characteristics for AC
T
A
= +25°C
Symbol
V
IH
T
A
= −40°C
to
+85°C
Units
V
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.46
3.76
4.76
0.1
0.1
0.1
0.44
0.44
0.44
±1.0
75
−75
µA
mA
mA
µA
µA
V
V
V
Parameter
Minimum HIGH Level
Input Voltage
V
CC
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
Conditions
V
OUT
=
0.1V or
V
CC
– 0.1V
V
OUT
=
0.1V or
V
CC
– 0.1V
I
OUT
=
–50µA
Typ.
1.5
2.25
2.75
1.5
2.25
2.75
2.99
4.49
5.49
2.1
Guaranteed Limits
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.56
3.86
4.86
V
IL
Maximum LOW Level
Input Voltage
V
OH
Minimum HIGH Level
Output Voltage
V
IN
=
V
IL
or V
IH
,
I
OH
=
–12mA
V
IN
=
V
IL
or V
IH
,
I
OH
=
–24mA
V
IN
=
V
IL
or V
IH
,
I
OH
=
–24mA
(1)
0.002
0.001
0.001
V
IN
=
V
IL
or V
IH
,
I
OL
=
12mA
V
IN
=
V
IL
or V
IH
,
I
OL
=
24mA
V
IN
=
V
IL
or V
IH
,
I
OL
=
24mA
(1)
V
I
=
V
CC
, GND
V
OLD
=
1.65V Max.
V
OHD
=
3.85V Min.
V
IN
=
V
CC
or GND
V
I
(OE)
=
V
IL
, V
IH
;
V
I
=
V
CC
, GND;
V
O
=
V
CC
, GND
I
OUT
=
50µA
V
OL
Maximum LOW Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
0.1
0.1
0.1
0.36
0.36
0.36
±0.1
I
IN(2)
I
OLD
I
OHD
I
CC(2)
I
OZT
Maximum Input
Leakage Current
Minimum Dynamic
Output Current
(3)
Maximum Quiescent
Supply Current
Maximum I/O
Leakage Current
5.5
5.5
5.5
5.5
5.5
4.0
±0.3
40.0
±3.0
Notes:
1. All outputs loaded; thresholds on input associated with output under test.
2. I
IN
and I
CC
@ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V
CC
.
3. Maximum test duration 2.0ms, one output loaded at a time.
©1988 Fairchild Semiconductor Corporation
74AC299, 74ACT299 Rev. 1.4.0
www.fairchildsemi.com
5
TI技术论坛
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
