Freescale Semiconductor
Addendum
Document Number: QFN_Addendum
Rev. 0, 07/2014
Addendum for New QFN
Package Migration
This addendum provides the changes to the 98A case outline numbers for products covered in this book.
Case outlines were changed because of the migration from gold wire to copper wire in some packages. See
the table below for the old (gold wire) package versus the new (copper wire) package.
To view the new drawing, go to Freescale.com and search on the new 98A package number for your
device.
For more information about QFN package use, see EB806:
Electrical Connection Recommendations for
the Exposed Pad on QFN and DFN Packages.
© Freescale Semiconductor, Inc., 2014. All rights reserved.
MC9S08AC60 Series Features
8-Bit HCS08 Central Processor Unit (CPU)
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40-MHz HCS08 CPU (central processor unit)
20-MHz internal bus frequency
HC08 instruction set with added BGND instruction
Background debugging system
Breakpoint capability to allow single breakpoint
setting during in-circuit debugging (plus two more
breakpoints in on-chip debug module)
On-chip in-circuit emulator (ICE) Debug module
containing two comparators and nine trigger
modes. Eight deep FIFO for storing
change-of-flow addresses and event-only data.
Supports both tag and force breakpoints.
Support for up to 32 interrupt/reset sources
Up to 60 KB of on-chip FLASH memory with
security options
Up to 2 KB of on-chip RAM
Clock source options include crystal, resonator,
external clock, or internally generated clock with
precision NVM trimming using ICG module
Optional watchdog computer operating properly
(COP) reset with option to run from independent
1kHz internal clock source or bus clock
Low-voltage detection with reset or interrupt
Illegal opcode detection with reset
Cyclic Redundancy Check (CRC) Module to
support fast cyclic redundancy checks on
memory.
Wait plus two stops
Peripherals
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ADC
— Up to 16-channel, 10-bit analog-to-digital
converter with automatic compare function
SCI
— Two serial communications interface
modules with optional 13-bit break. supports LIN
2.0 Protocol and SAE J2602; Master extended
break generation; Slave extended break detection
SPI
— Serial peripheral interface module
IIC
— Inter-integrated circuit bus module to
operate at up to 100 kbps with maximum bus
loading; capable of higher baudrates with reduced
loading. 10-bit address extension option.
Timers
— Up to two 2-channel and one 6-channel
16-bit timer/pulse-width modulator (TPM) module:
Selectable input capture, output compare, and
edge-aligned PWM capability on each channel.
Each timer module may be configured for
buffered, centered PWM (CPWM) on all channels
KBI
— Up to 8-pin keyboard interrupt module
CRC
- Hardware CRC generation using a 16-bit
shift register
Up to 54 general-purpose input/output (I/O) pins
Software selectable pullups on ports when used
as inputs
Software selectable slew rate control on ports
when used as outputs
Software selectable drive strength on ports when
used as outputs
Master reset pin and power-on reset (POR)
Internal pullup on RESET, IRQ, and BKGD/MS
pins to reduce customer system cost
64-pin quad flat package (QFP)
64-pin low-profile quad flat package (
LQFP
)
48-pin quad flat pack no lead package (QFN)
44-pin low-profile quad flat package (LQFP)
32-pin low-profile quad flat package (LQFP)
Development Support
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Memory Options
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Clock Source Options
Input/Output
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System Protection
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Package Options
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Power-Saving Modes
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DSP 与 ARM 处理器
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