MC74HC390A
Dual 4-Stage Binary Ripple
Counter with
÷
2 and
÷
5
Sections
High−Performance Silicon−Gate CMOS
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The MC74HC390A is identical in pinout to the LS390. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of two independent 4−bit counters, each
composed of a divide−by−two and a divide−by−five section. The
divide−by−two and divide−by−five counters have separate clock
inputs, and can be cascaded to implement various combinations of
÷
2
and/or
÷
5 up to a
÷
100 counter.
Flip−flops internal to the counters are triggered by high−to−low
transitions of the clock input. A separate, asynchronous reset is
provided for each 4−bit counter. State changes of the Q outputs do not
occur simultaneously because of internal ripple delays. Therefore,
decoded output signals are subject to decoding spikes and should not
be used as clocks or strobes except when gated with the Clock of the
HC390A.
Features
SOIC−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F
PIN ASSIGNMENT
CLOCK A
a
RESET a
Q
Aa
CLOCK B
a
Q
Ba
Q
Ca
Q
Da
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
CLOCK A
b
RESET b
Q
Ab
CLOCK B
b
Q
Bb
Q
Cb
Q
Db
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1
mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No 7 A
•
Chip Complexity: 244 FETs or 61 Equivalent Gates
•
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
•
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
MARKING DIAGRAMS
16
HC390AG
AWLYWW
1
SOIC−16
A
L, WL
Y, YY
W, WW
G or
G
1
TSSOP−16
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
16
HC
390A
ALYWG
G
(Note: Microdot may be in either location)
÷
2
COUNTER
3, 13
CLOCK A
1, 15
FUNCTION TABLE
Q
A
Clock
A
X
B
X
X
X
PIN 16 = V
CC
PIN 8 = GND
Reset
H
L
L
Action
Reset
÷
2 and
÷
5
Increment
÷
2
Increment
÷
5
5, 11
CLOCK B
4, 12
÷
5
COUNTER
Q
B
6, 10
Q
C
7, 9
Q
D
RESET
2, 14
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
Figure 1. Logic Diagram
©
Semiconductor Components Industries, LLC, 2014
1
August, 2014 − Rev. 7
Publication Order Number:
MC74HC390A/D
MC74HC390A
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MAXIMUM RATINGS
Symbol
V
CC
V
in
I
in
V
out
I
out
P
D
Parameter
Value
Unit
V
V
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Voltage (Referenced to GND)
DC Output Current, per Pin
–0.5 to +7.0
–0.5 to V
CC
+ 0.5
–0.5 to V
CC
+ 0.5
±20
±25
±50
mA
mA
mA
I
CC
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air,
Storage Temperature
SOIC Package†
TSSOP Package†
500
450
mW
_C
_C
T
stg
T
L
–65 to +150
260
Lead Temperature, 1 mm from Case for 10 Seconds
SOIC or TSSOP Package
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating: SOIC Package: –7 mW/_C from 65_ to 125_C
TSSOP Package: −6.1 mW/_C from 65_ to 125_C
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND
v
(V
in
or V
out
)
v
V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
in
, V
out
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time
(Figure 1)
V
CC
= 2.0 V
V
CC
= 3.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Min
2.0
0
–55
0
0
0
0
Max
6.0
V
CC
+125
1000
600
500
400
Unit
V
V
_C
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Guaranteed Limit
Symbol
V
IH
Parameter
Minimum High−Level Input
Voltage
Test Conditions
V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
|
v
20
mA
V
CC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
4.5
6.0
|I
out
|
v
2.4 mA
|I
out
|
v
4.0 mA
|I
out
|
v
5.2 mA
3.0
4.5
6.0
2.0
4.5
6.0
|I
out
|
v
2.4 mA
|I
out
|
v
4.0 mA
|I
out
|
v
5.2 mA
3.0
4.5
6.0
–55 to
25_C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.48
3.98
5.48
0.1
0.1
0.1
0.26
0.26
0.26
v85_C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.34
3.84
5.34
0.1
0.1
0.1
0.33
0.33
0.33
v125_C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.20
3.70
5.20
0.1
0.1
0.1
0.40
0.40
0.40
V
Unit
V
V
IL
Maximum Low−Level Input
Voltage
V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
|
v
20
mA
V
V
OH
Minimum High−Level Output
Voltage
V
in
= V
IH
or V
IL
|I
out
|
v
20
mA
V
in
= V
IH
or V
IL
V
V
OL
Maximum Low−Level Output
Voltage
V
in
= V
IH
or V
IL
|I
out
|
v
20
mA
V
in
= V
IH
or V
IL
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2
MC74HC390A
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND) (continued)
Guaranteed Limit
Symbol
I
in
I
CC
Parameter
Maximum Input Leakage
Current
Maximum Quiescent Supply
Current (per Package)
Test Conditions
V
in
= V
CC
or GND
V
in
= V
CC
or GND
I
out
= 0
mA
V
CC
V
6.0
6.0
–55 to
25_C
±0.1
4
v85_C
±1.0
40
v125_C
±1.0
160
Unit
mA
mA
AC ELECTRICAL CHARACTERISTICS
(C
L
= 50 pF, Input t
f
= t
f
= 6 ns)
Guaranteed Limit
Symbol
f
max
Parameter
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 3)
V
CC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
−
–55 to
25_C
10
15
30
50
70
40
24
20
200
160
58
49
70
40
26
22
90
56
37
31
70
40
26
22
80
48
30
26
75
27
15
13
10
v85_C
9
14
28
45
80
45
30
26
250
185
65
62
80
45
33
28
105
70
46
39
80
45
33
28
95
65
38
33
95
32
19
15
10
v125_C
8
12
25
40
90
50
36
31
300
210
70
68
90
50
39
33
180
100
56
48
90
50
39
33
110
75
44
39
110
36
22
19
10
Unit
MHz
t
PLH
,
t
PHL
Maximum Propagation Delay, Clock A to QA
(Figures 1 and 3)
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Clock A to QC
(QA connected to Clock B)
(Figures 1 and 3)
Maximum Propagation Delay, Clock B to QB
(Figures 1 and 3)
ns
t
PLH
,
t
PHL
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Clock B to QC
(Figures 1 and 3)
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Clock B to QD
(Figures 1 and 3)
ns
t
PHL
Maximum Propagation Delay, Reset to any Q
(Figures 2 and 3)
ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
ns
C
in
Maximum Input Capacitance
pF
Typical @ 25°C, V
CC
= 5.0 V
C
PD
Power Dissipation Capacitance (Per Counter)*
35
pF
* Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC2
f + I
CC
V
CC
.
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3
MC74HC390A
TIMING REQUIREMENTS
(Input t
r
= t
f
= 6 ns)
Guaranteed Limit
Symbol
t
rec
Parameter
Minimum Recovery Time, Reset Inactive to Clock A or Clock B
(Figure 3)
V
CC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
–55 to
25_C
25
15
10
9
75
27
15
13
75
27
20
18
1000
800
500
400
v85_C
30
20
13
11
95
32
19
15
95
32
24
22
1000
800
500
400
v125_C
40
30
15
13
110
36
22
19
110
36
30
28
1000
800
500
400
Unit
ns
t
w
Minimum Pulse Width, Clock A, Clock B
(Figure 2)
ns
t
w
Minimum Pulse Width, Reset
(Figure 3)
ns
t
f
, t
f
Maximum Input Rise and Fall Times
(Figure 2)
ns
PIN DESCRIPTIONS
INPUTS
Clock A (Pins 1, 15) and Clock B (Pins 4, 15)
OUTPUTS
Q
A
(Pins 3, 13)
Clock A is the clock input to the
÷
2 counter; Clock B is
the clock input to the
÷
5 counter. The internal flip−flops are
toggled by high−to−low transitions of the clock input.
CONTROL INPUTS
Reset (Pins 2, 14)
Output of the
÷
2 counter.
Q
B
, Q
C
, Q
D
(Pins 5, 6, 7, 9, 10, 11)
Asynchronous reset. A high at the Reset input prevents
counting, resets the internal flip−flops, and forces Q
A
through Q
D
low.
Outputs of the
÷
5 counter. Q
D
is the most significant bit.
Q
A
is the least significant bit when the counter is connected
for BCD output as in Figure 5. Q
B
is the least significant bit
when the counter is operating in the bi−quinary mode as in
Figure 6.
SWITCHING WAVEFORMS
t
f
90%
50%
10% 10%
t
w
1/f
max
t
PLH
Q
90%
50%
10%
t
TLH
t
THL
CLOCK
t
PHL
Q
t
r
V
CC
GND
RESET
t
PHL
50%
t
rec
50%
GND
50%
GND
t
w
V
CC
CLOCK
V
CC
Figure 2.
Figure 3.
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4
MC74HC390A
TEST CIRCUIT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
C
L
*
*Includes all probe and jig capacitance
Figure 4.
EXPANDED LOGIC DIAGRAM
CLOCK A
1, 15
C
D
R
Q
Q
3, 13
Q
A
CLOCK B
4, 12
D
C
R
Q
Q
5, 11
Q
B
C
D
R
Q
Q
6, 10 Q
C
C
D
RESET
2, 14
R
Q
7, 9 Q
D
TIMING DIAGRAM
(Q
A
Connected to Clock B)
0
CLOCK A
RESET
Q
A
Q
B
Q
C
Q
D
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
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